Altera Cyclone IV Manuals

Manuals and User Guides for Altera Cyclone IV. We have 1 Altera Cyclone IV manual available for free PDF download: Device Handbook

Altera Cyclone IV Device Handbook

Altera Cyclone IV Device Handbook (490 pages)

Brand: Altera | Category: Computer Hardware | Size: 17.62 MB

Table of Contents

Table of Contents

3
- Chapter Revision Dates
  9
- Additional Information
  11
  - How to Contact Altera
    11
  - Typographic Conventions
    11
- Section I. Device Core
  13
- Chapter 1. Cyclone IV FPGA Device Family Overview
  
  15
  - Cyclone IV Device Family Features
    15
  - Device Resources
    17
  - Package Matrix
    19
  - Cyclone IV Device Family Speed Grades
    21
  - Cyclone IV Device Family Architecture
    22
    
    FPGA Core Fabric
    22
    
    Clock Management
    23
    
    External Memory Interfaces
    23
    
    I/O Features
    23
    
    Configuration
    24
    
    High-Speed Transceivers (Cyclone IV GX Devices Only)
    24
    
    Hard IP for PCI Express (Cyclone IV GX Devices Only)
    25
  - Reference and Ordering Information
    26
  - Document Revision History
    27
  - Logic Elements
    29
    
    LE Features
    30
  - LE Operating Modes
    31
    
    Normal Mode
    31
    
    Arithmetic Mode
    32
  - Logic Array Blocks
    33
    
    Topology
    33
    
    LAB Interconnects
    34
  - LAB Control Signals
    34
  - Document Revision History
    35
- Chapter 3. Memory Blocks in Cyclone IV Devices
  
  37
  - Overview
    37
    
    Byte Enable Support
    39
    
    Control Signals
    39
    
    Parity Bit Support
    39
    
    Packed Mode Support
    40
    
    Address Clock Enable Support
    41
    
    Mixed-Width Support
    42
    
    Asynchronous Clear
    43
  - Memory Modes
    43
    
    Single-Port Mode
    44
    
    Simple Dual-Port Mode
    45
    
    True Dual-Port Mode
    47
    
    Shift Register Mode
    48
    
    FIFO Buffer Mode
    49
    
    ROM Mode
    49
  - Clocking Modes
    50
    
    Independent Clock Mode
    50
    
    Input or Output Clock Mode
    50
    
    Read or Write Clock Mode
    51
    
    Single-Clock Mode
    51
  - Design Considerations
    51
    
    Read-During-Write Operations
    51
    
    Mixed-Port Read-During-Write Mode
    52
    
    Same-Port Read-During-Write Mode
    52
    
    Conflict Resolution
    53
    
    Power Management
    54
    
    Power-Up Conditions and Memory Initialization
    54
  - Document Revision History
    54
- Chapter 4 . Embedded Multipliers in Cyclone IV Devices
  
  55
  - Embedded Multiplier Block Overview
    55
  - Architecture
    56
    
    Input Registers
    57
    
    Multiplier Stage
    57
    
    Output Registers
    58
  - Operational Modes
    58
    
    18-Bit Multipliers
    59
    
    9-Bit Multipliers
    60
  - Document Revision History
    61
- Chapter 5 . Clock Networks and Plls in Cyclone IV Devices
  
  63
  - Clock Networks
    63
    
    GCLK Network
    64
    
    Clock Control Block
    72
    
    GCLK Network Clock Source Generation
    74
    
    Clkena Signals
    78
    
    GCLK Network Power down
    78
  - Plls in Cyclone IV Devices
    80
  - Cyclone IV PLL Hardware Overview
    82
    
    External Clock Outputs
    83
  - Clock Feedback Modes
    85
    
    Source-Synchronous Mode
    85
    
    No Compensation Mode
    86
    
    Normal Mode
    86
    
    Zero Delay Buffer Mode
    87
    
    Deterministic Latency Compensation Mode
    88
  - Hardware Features
    88
    
    Clock Multiplication and Division
    88
    
    PLL Control Signals
    89
    
    Post-Scale Counter Cascading
    89
    
    Programmable Duty Cycle
    89
    
    Automatic Clock Switchover
    90
    
    Clock Switchover
    90
    
    Manual Override
    91
    
    Guidelines
    92
    
    Manual Clock Switchover
    92
  - Programmable Bandwidth
    94
  - Phase Shift Implementation
    94
  - PLL Cascading
    95
  - PLL Reconfiguration
    96
    
    PLL Reconfiguration Hardware Implementation
    96
    
    Post-Scale Counters (C0 to C4)
    98
    
    Scan Chain Description
    99
    
    Charge Pump and Loop Filter
    100
    
    Bypassing a PLL Counter
    101
    
    Dynamic Phase Shifting
    101
  - Spread-Spectrum Clocking
    103
  - PLL Specifications
    103
  - Document Revision History
    104
  - Section II. I/O Interfaces
    105
- Chapter 6. I/O Features in Cyclone IV Devices
  
  105
  - Cyclone IV I/O Elements
    108
  - I/O Element Features
    109
    
    Programmable Current Strength
    109
    
    Bus Hold
    110
    
    Open-Drain Output
    110
    
    Slew Rate Control
    110
    
    Programmable Delay
    111
    
    Programmable Pull-Up Resistor
    111
    
    PCI-Clamp Diode
    112
  - OCT Support
    112
    
    On-Chip Series Termination with Calibration
    114
    
    On-Chip Series Termination Without Calibration
    116
  - I/O Standards
    117
  - Termination Scheme for I/O Standards
    119
    
    Voltage-Referenced I/O Standard Termination
    120
    
    Differential I/O Standard Termination
    121
  - I/O Banks
    122
    
    High-Speed Differential Interfaces
    128
    
    External Memory Interfacing
    129
  - Pad Placement and DC Guidelines
    129
    
    DC Guidelines
    129
    
    Pad Placement
    129
  - Clock Pins Functionality
    129
  - High-Speed I/O Interface
    130
  - High-Speed I/O Standards Support
    134
    
    High Speed Serial Interface (HSSI) Input Reference Clock Support
    134
    
    LVDS I/O Standard Support in Cyclone IV Devices
    135
    
    BLVDS I/O Standard Support in Cyclone IV Devices
    136
    
    Designing with LVDS
    136
    
    Designing with BLVDS
    137
    
    Designing with RSDS, Mini-LVDS, and PPDS
    138
    
    RSDS, Mini-LVDS, and PPDS I/O Standard Support in Cyclone IV Devices
    138
    
    LVPECL I/O Support in Cyclone IV Devices
    140
    
    Differential HSTL I/O Standard Support in Cyclone IV Devices
    141
    
    Differential SSTL I/O Standard Support in Cyclone IV Devices
    141
  - True Differential Output Buffer Feature
    141
    
    Programmable Pre-Emphasis
    141
  - High-Speed I/O Timing
    142
  - Design Guidelines
    143
    
    Differential Pad Placement Guidelines
    143
    
    Board Design Considerations
    144
  - Software Overview
    144
  - Document Revision History
    145
- Chapter 7. External Memory Interfaces in Cyclone IV Devices
  
  147
  - Cyclone IV Devices Memory Interfaces Pin Support
    148
    
    Data and Data Clock/Strobe Pins
    148
    
    Optional Parity, DM, and Error Correction Coding Pins
    157
    
    Address and Control/Command Pins
    158
    
    Memory Clock Pins
    158
  - Cyclone IV Devices Memory Interfaces Features
    158
    
    DDR Input Registers
    158
    
    DDR Output Registers
    160
    
    OCT with Calibration
    161
    
    Pll
    161
  - Document Revision History
    162
  - Section III. System Integration
    163
- Chapter 8. Configuration and Remote System Upgrades in Cyclone IV Devices
  
  163
  - Configuration
    165
    
    Configuration Data Decompression
    166
    
    Configuration Features
    166
    
    Configuration Requirement
    167
    
    Configuration File Size
    168
    
    Power-On Reset (POR) Circuit
    168
    
    Configuration and JTAG Pin I/O Requirements
    169
    
    Configuration
    170
    
    Configuration Process
    170
    
    Power up
    170
    
    Reset
    170
    
    Configuration Error
    171
    
    Initialization
    171
    
    User Mode
    171
    
    Configuration Scheme
    172
    
    AS Configuration (Serial Configuration Devices)
    174
    
    Single-Device as Configuration
    174
    
    Multi-Device as Configuration
    177
    
    Configuring Multiple Cyclone IV Devices with the same Design
    178
    
    Programming Serial Configuration Devices
    183
    
    AP Configuration (Supported Flash Memories)
    185
    
    AP Configuration Supported Flash Memories
    186
    
    Single-Device AP Configuration
    187
    
    Multi-Device AP Configuration
    189
    
    Byte-Wide Multi-Device AP Configuration
    190
    
    Word-Wide Multi-Device AP Configuration
    190
    
    Configuring with Multiple Bus Masters
    192
    
    Guidelines for Connecting Parallel Flash to Cyclone IV E Devices for an AP Interface
    192
    
    Estimating AP Configuration Time
    194
    
    Programming Parallel Flash Memories
    195
    
    PS Configuration
    196
    
    PS Configuration Using an External Host
    197
    
    PS Configuration Timing
    200
    
    PS Configuration Using a Download Cable
    201
    
    FPP Configuration
    204
    
    FPP Configuration Using an External Host
    204
    
    FPP Configuration Timing
    208
    
    JTAG Configuration
    209
    
    Configuring Cyclone IV Devices with Jam STAPL
    216
    
    Configuring Cyclone IV Devices with the Jrunner Software Driver
    216
    
    Combining JTAG and as Configuration Schemes
    217
    
    Programming Serial Configuration Devices In-System with the JTAG Interface
    219
    
    JTAG Instructions
    221
    
    Device Configuration Pins
    226
  - Remote System Upgrade
    233
    
    Functional Description
    233
    
    Configuration Image Types
    234
    
    Enabling Remote Update
    234
    
    Remote System Upgrade Mode
    235
    
    Remote Update Mode
    235
    
    Dedicated Remote System Upgrade Circuitry
    238
    
    Remote System Upgrade Registers
    239
    
    Remote System Upgrade State Machine
    242
    
    User Watchdog Timer
    243
    
    Quartus II Software Support
    244
  - Document Revision History
    244
- Chapter 9. SEU Mitigation in Cyclone IV Devices
  
  247
  - Configuration Error Detection
    247
  - User Mode Error Detection
    248
  - Automated SEU Detection
    249
  - CRC_ERROR Pin
    249
  - Error Detection Block
    250
    
    Error Detection Registers
    250
  - Error Detection Timing
    251
  - Software Support
    252
    
    Accessing Error Detection Block through User Logic
    253
  - Recovering from CRC Errors
    255
  - Document Revision History
    256
- Chapter 10. JTAG Boundary-Scan Testing for Cyclone IV Devices
  
  257
  - IEEE Std. 1149.6 Boundary-Scan Register
    258
  - BST Operation Control
    259
    
    Extest_Pulse
    261
    
    Extest_Train
    261
  - I/O Voltage Support in a JTAG Chain
    261
  - Boundary-Scan Description Language Support
    262
  - Document Revision History
    263
- Chapter 11 . Power Requirements for Cycloneiv Devices
  
  265
  - External Power Supply Requirements
    265
  - Hot-Socketing Specifications
    266
    
    Devices Driven before Power-Up
    266
    
    I/O Pins Remain Tri-Stated During Power-Up
    266
  - Hot-Socketing Feature Implementation
    267
  - Power-On Reset Circuitry
    267
  - Document Revision History
    268
Table of Contents

271
- Chapter Revision Dates
  275
- Additional Information
  277
  - How to Contact Altera
    277
  - Typographic Conventions
    277
- Section I. Transceivers
  279
- Chapter 1. Cyclone IV Transceivers Architecture Transceiver Architecture
  283
  - Architectural Overview
    284
  - Byte Serializer
    285
  - Transmitter Channel Datapath
    285
  - TX Phase Compensation FIFO
    285
  - 8B/10B Encoder
    286
  - Miscellaneous Transmitter PCS Features
    288
  - Serializer
    289
  - Transmitter Output Buffer
    290
  - Receiver Channel Datapath
    291
  - Receiver Input Buffer
    291
  - Automatic Lock Mode
    295
  - Clock Data Recovery
    295
  - Deserializer
    296
  - Manual Lock Mode
    296
  - Word Aligner
    297
  - Deskew FIFO
    302
  - 8B/10B Decoder
    303
  - Rate Match FIFO
    303
  - Byte Deserializer
    304
  - Byte Ordering
    304
  - Miscellaneous Receiver PCS Feature
    305
  - RX Phase Compensation FIFO
    305
  - Transceiver Clocking Architecture
    306
  - Input Reference Clocking
    307
  - Transceiver Channel Datapath Clocking
    309
  - Non-Bonded Channel Configuration
    311
  - Bonded Channel Configuration
    317
  - FPGA Fabric-Transceiver Interface Clocking
    323
  - Calibration Block
    325
  - PCI-Express Hard IP Block
    326
  - Transceiver Functional Modes
    327
  - Basic Mode
    328
  - Additional Options in Basic Mode
    330
  - Rate Match FIFO Operation in Basic Mode
    330
  - PCI Express (PIPE) Mode
    332
  - PIPE Interface
    334
  - Receiver Detection Circuitry
    334
  - Electrical Idle Control
    335
  - Clock Rate Compensation
    336
  - Lane Synchronization
    336
  - Low-Latency Synchronous Pcie
    336
  - Signal Detect at Receiver
    336
  - Compliance Pattern Transmission
    337
  - Electrical Idle Inference
    337
  - Fast Recovery from P0S State
    337
  - GIGE Mode
    338
  - Reset Requirement
    338
  - Lane Synchronization
    342
  - Running Disparity Preservation with Idle Ordered Set
    342
  - Clock Frequency Compensation
    343
  - Serial Rapidio Mode
    344
  - Lane Synchronization
    346
  - Clock Frequency Compensation
    347
  - XAUI Mode
    347
  - XGMII and PCS Code Conversions
    350
  - Channel Deskewing
    351
  - Lane Synchronization
    352
  - Clock Rate Compensation
    353
  - Deterministic Latency Mode
    353
  - Registered Mode Phase Compensation FIFO
    355
  - PLL PFD Feedback
    356
  - Receive Bit-Slip Indication
    356
  - SDI Mode
    356
  - Transmit Bit-Slip Control
    356
  - Loopback
    358
  - Reverse Parallel Loopback
    359
  - Serial Loopback
    359
  - Reverse Serial Loopback
    360
  - Self Test Modes
    361
  - Bist
    362
  - Prbs
    363
  - Transceiver Top-Level Port Lists
    365
  - Document Revision History
    373
- Chapter 2. Cyclone IV Reset Control and Power down
  
  376
Table of Contents

439
- Chapter Revision Dates
  441
- Additional Information
  443
  - How to Contact Altera
    443
  - Typographic Conventions
    443
- Chapter 1. Cyclone IV Device Datasheet
  445
  - OCT Specifications
    454
  - Pin Capacitance
    456
  - Internal Weak Pull-Up and Weak Pull-Down Resistor
    457
  - Hot-Socketing
    457
  - Schmitt Trigger Input
    458
    
    I/O Standard Specifications
    458
  - Power Consumption
    462
  - Switching Characteristics
    462
    
    Transceiver Performance Specifications
    463
    
    Clock Tree Specifications
    469
    
    Core Performance Specifications
    469
    
    PLL Specifications
    470
    
    Configuration and JTAG Specifications
    472
    
    Embedded Multiplier Specifications
    472
    
    Memory Block Specifications
    472
    
    Periphery Performance
    473
    
    External Memory Interface Specifications
    478
    
    Duty Cycle Distortion Specifications
    479
    
    OCT Calibration Timing Specification
    479
    
    IOE Programmable Delay
    480
  - Glossary
    483
  - Document Revision History
    488
- Section I. Device Datasheet
  445

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