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Fujitsu F2MC-8L MB89125A manual available for free PDF download: Hardware Manual
Fujitsu F2MC-8L MB89125A Hardware Manual (373 pages)
8-BIT MICROCONTROLLER
Brand:
Fujitsu
| Category:
Microcontrollers
| Size: 1.71 MB
Table of Contents
Table of Contents
14
Chapter 1 Overview
28
MB89120/120A Series Features
29
MB89120/120A Series Product Lineup
31
Table 1.2-1 MB89120/120A Series Product Lineup
31
Table 1.2-2 CPU and Peripheral Functions for MB89120/120A Series
31
Differences Among Products
33
Table 1.3-1 Package and Corresponding Products
33
MB89120/120A Series Block Diagram
35
Figure 1.4-1 MB89120/120A Series Block Diagram
35
Pin Assignment
36
Figure 1.5-1 FTP-48P-M13 Pin Assignment
36
Figure 1.5-2 DIP-48P-M01 Pin Assignment
37
Figure 1.5-3 MQP-48C-P01 Pin Assignment
38
Package Dimensions
39
Figure 1.6-1 FPT-48P-M13 Package Dimensions
39
Figure 1.6-2 DIP-48P-M01 Package Dimensions
40
Figure 1.6-3 MQP-48C-P01 Package Dimensions
41
Pin Functions
42
Table 1.7-1 Pin Description
42
Table 1.7-2 Pin Description for External EPROM Pins (MB89PV130A Only)
43
I/O Circuit Types
45
Table 1.8-1 I/O Circuit Type
45
Chapter 2 Handling Devices
48
Notes on Handling Devices
49
Chapter 3 Cpu
52
Memory Space
53
Figure 3.1-1 Memory Map
54
Special Areas
55
Table 3.1-1 General-Purpose Register Area
55
Table 3.1-2 Vector Table
55
Figure 3.1-2 Allocation 16-Bit Data in Memory
57
Figure 3.1-3 Allocation of 16-Bit Data in an Instruction
57
Storing 16-Bit Data in Memory
57
Dedicated Registers
59
Figure 3.2-1 Dedicated Register Configuration
59
Condition Code Register (CCR)
61
Figure 3.2-2 Structure of Condition Code Register
61
Figure 3.2-3 Change of Carry Flag by Shift Instruction
62
Figure 3.2-4 Structure of Register Bank Pointer
64
Figure 3.2-5 Rule for Conversion of Actual Addresses of General-Purpose Register Area
64
Register Bank Pointer (RP)
64
General-Purpose Registers
65
Figure 3.3-1 Register Bank Structure
65
Interrupts
67
Table 3.2-1 Interrupt Level
67
Table 3.4-1 Interrupt Request and Interrupt Vector
67
Figure 3.4-1 Structure of Interrupt Level Setting Registers
69
Interrupt Level Setting Registers (ILR1, ILR2, ILR3)
69
Table 3.4-2 Interrupt Level Setting Bit and Interrupt Level
69
Interrupt Processing
71
Figure 3.4-2 Interrupt Processing
72
Figure 3.4-3 Example of Multiple Interrupts
74
Multiple Interrupts
74
Figure 3.4-4 Interrupt Processing Time
76
Interrupt Processing Time
76
Figure 3.4-5 Stack Operation at Start of Interrupt Processing
78
Stack Operation During Interrupt Processing
78
Figure 3.4-6 Stack Area for Interrupt Processing
79
Stack Area for Interrupt Processing
79
Resets
80
Table 3.5-1 Reset Source
80
Table 3.5-2 Reset Source and Oscillation Stabilization Delay Time
81
External Reset Pin
82
Figure 3.5-1 Block Diagram of External Reset Pin
82
Figure 3.5-2 Reset Operation Flowchart
83
Reset Operation
83
Pin States During Reset
85
Clocks
86
Figure 3.6-1 Clock Supply Map
87
Clock Generator
88
Figure 3.6-2 Connection Example for Crystal or Ceramic Resonator
88
Figure 3.6-3 Connection Example for External Clock
89
Clock Controller
90
Figure 3.6-4 Block Diagram of Clock Controller
90
Figure 3.6-5 System Clock Control Register (SYCC)
92
System Clock Control Register (SYCC)
92
Table 3.6-1 System Clock Control Register (SYCC) Bits
93
Clock Modes
95
Table 3.6-2 Operating States in each Clock Mode
95
Figure 3.6-6 Operation of an Oscillator after Starting Oscillation
98
Oscillation Stabilization Delay Time
98
Table 3.6-3 Main Clock Mode Operation Start Conditions and Oscillation Stabilization Delay Time
99
Standby Modes (Low-Power Consumption)
100
Standby Mode Operating States
102
Table 3.7-1 Operating States of the CPU and Peripheral Functions in Standby Mode
102
Sleep Mode
104
Stop Mode
105
Watch Mode
107
Standby Control Register (STBC)
108
Figure 3.7-1 Standby Control Register (STBC)
108
Table 3.7-2 Standby Control Register (STBC) Bits
109
State Transition Diagram 1 (Product with Power-On Reset Function in Dual-Clock Configuration)
110
Figure 3.7-2 State Transition Diagram 1 (Product with Power-On Reset Function in Dual-Clock Configuration)
110
Table 3.7-3 Switching to and from Clock Mode (Product with Power-On Reset Function in Dual-Clock Configuration)
111
Table 3.7-4 Switching to and from Standby Mode (Product with Power-On Reset Function in Dual-Clock Configuration)
111
State Transition Diagram 2 (Product Without Power-On Reset Function in Dual-Clock Configuration)
113
Figure 3.7-3 State Transition Diagram 2 (Product Without Power-On Reset Function in Dual-Clock Configuration)
113
State Transition Diagram 3 (Products in Single-Clock Configuration)
116
Figure 3.7-4 State Transition Diagram 3 (Product with Power-On Reset Function)
116
Figure 3.7-5 State Transition Diagram 3 (Product Without Power-On Reset Function)
116
Table 3.7-7 Switching to Main Clock Mode Run State and Reset (Product in Single-Clock Configuration)
117
Table 3.7-8 Switching to and from Standby Mode (Product in Single-Clock Configuration)
117
Pin States in Standby Modes
118
Table 3.7-9 Pin States in Standby Modes
118
3.7.10 Notes on Using Standby Modes
120
Table 3.7-10 Low-Power Consumption Mode Settings in Standby Control Register (STBC)
121
Memory Access Modes
122
Figure 3.8-1 Mode Data Structure
122
Table 3.8-1 Mode Pin Setting
122
Figure 3.8-2 Memory Access Selection Operation
123
Table 3.8-2 Mode Pins and Mode Data
123
Chapter 4 I/O Ports
124
Overview of I/O Ports
125
Table 4.1-1 Port Function
125
Table 4.1-2 Port Registers
126
Port 0
127
Table 4.2-1 Port 0 Pins
128
Figure 4.2-1 Block Diagram of Port 0 Pin
129
Table 4.2-2 Correspondence between Pins and Registers for Port 0
129
Port 0 Registers (PDR0, DDR0)
130
Table 4.2-3 Port 0 Register Functions
130
Operation of Port 0
132
Table 4.2-4 Port 0 Pin States
133
Port 1
134
Table 4.3-1 Port 1 Pins
134
Figure 4.3-1 Block Diagram of Port 1 Pin
135
Table 4.3-2 Correspondence between Pins and Registers for Port 1
135
Port 1 Registers (PDR1, DDR1)
136
Table 4.3-3 Port 1 Register Functions
136
Operation of Port 1
138
Table 4.3-4 Port 1 Pin States
139
Port 2
140
Table 4.4-1 Port 2 Pin
140
Figure 4.4-1 Block Diagram of Port 2 Pin
141
Table 4.4-2 Correspondence between Pins and Register for Port 2
141
Port 2 Register (PDR2)
142
Table 4.4-3 Port 2 Register Function
142
Operation of Port 2
143
Table 4.4-4 Port 2 Pin State
143
Port 3
144
Table 4.5-1 Port 3 Pins
144
Figure 4.5-1 Block Diagram of Port 3 Pins (P30 to P32, P34 to P36)
145
Figure 4.5-2 Block Diagram of Port 3 Pins (P33, P37)
145
Table 4.5-2 Correspondence between Pins and Registers for Port 3
146
Port 3 Registers (PDR3, DDR3)
147
Table 4.5-3 Port 3 Register Function
148
Operation of Port 3
149
Table 4.5-4 Port 3 Pin State
150
Port 4
151
Table 4.6-1 Port 4 Pins
151
Figure 4.6-1 Block Diagram of Port 4 Pin
152
Table 4.6-2 Correspondence between Pins and Register for Port 4
152
Port 4 Register (PDR4)
153
Table 4.6-3 Port 4 Register Function
153
Operation of Port 4
154
Table 4.6-4 Port 4 Pin State
154
Program Example for I/O Ports
155
Figure 4.7-1 Connection Example for an Eight-Segment LED
155
Chapter 5 Timebase Timer
158
Overview of Timebase Timer
159
Table 5.1-1 Timebase Timer Interval Time
159
Table 5.1-2 Clock Supplied by Timebase Timer
159
Structure of Timebase Timer
161
Figure 5.2-1 Block Diagram of Timebase Timer
161
Timebase Timer Control Register (TBTC)
163
Figure 5.3-1 Timebase Timer Control Register (TBTC)
163
Table 5.3-1 Timebase Timer Control Register (TBTC) Bits
163
Timebase Timer Interrupt
165
Table 5.4-1 Register and Vector Table for Timebase Timer Interrupt
165
Operation of Timebase Timer
166
Figure 5.5-1 Interval Timer Function Settings
166
Figure 5.5-2 Timebase Timer Operation
167
Notes on Using Timebase Timer
168
Figure 5.6-1 Effect on Buzzer Output of Clearing Timebase Timer
169
Program Example for Timebase Timer
170
Chapter 6 Watchdog Timer
172
Overview of Watchdog Timer
173
Table 6.1-1 Watchdog Timer Interval Time
173
Structure of Watchdog Timer
174
Figure 6.2-1 Block Diagram of Watchdog Timer
174
Watchdog Timer Control Register (WDTC)
176
Figure 6.3-1 Watchdog Timer Control Register (WDTC)
176
Table 6.3-1 Watchdog Timer Control Register (WDTC) Bits
176
Operation of Watchdog Timer
178
Figure 6.4-1 Watchdog Timer Clear and Interval Time
179
Notes on Using Watchdog Timer
180
Program Example for Watchdog Timer
181
Chapter 7 8/16-Bit Timer/Counter
184
Overview of 8/16-Bit Timer/Counter
185
Table 7.1-1 Interval Time and Square Wave Output Ranges of Timer 1 in 8-Bit Mode
185
Table 7.1-2 Interval Time Ranges of Timer 2 in 8-Bit Mode
186
Table 7.1-3 Interval Time and Square Wave Output Ranges in 16-Bit Mode
186
Structure of 8/16-Bit Timer/Counter
188
Figure 7.2-1 Block Diagram of 8/16-Bit Timer/Counter
188
8/16-Bit Timer/Counter Pins
190
Figure 7.3-1 Block Diagram of 8/16-Bit Timer/Counter Pin (P33/EC/SCO)
191
Figure 7.3-2 Block Diagram of 8/16-Bit Timer/Counter Pin (P34/TO/INT0)
191
8/16-Bit Timer/Counter Registers
192
Figure 7.4-1 8/16-Bit Timer/Counter Registers
192
Figure 7.4-2 Timer 1 Control Register (T1CR)
193
Timer Control 1 Register (T1CR)
193
Table 7.4-1 Timer 1 Control Register (T1CR) Bits
194
Figure 7.4-3 Timer 2 Control Register (T2CR)
196
Timer Control 2 Register (T2CR)
196
Table 7.4-2 Timer 2 Control Register (T2CR) Bits
197
Figure 7.4-4 Timer 1 Data Register (T1DR)
198
Timer 1 Data Register (T1DR)
198
Figure 7.4-5 Timer 2 Data Register (T2DR)
200
Timer 2 Data Register (T2DR)
200
8/16-Bit Timer/Counter Interrupts
202
Table 7.5-1 8/16-Bit Timer/Counter Interrupt Control Flag Bits and Interrupt Source
202
Table 7.5-2 Register and Vector Table for 8/16-Bit Timer/Counter Interrupt
203
Operation of Interval Timer Function
204
Figure 7.6-1 Settings for Interval Timer Function (Timer 1)
204
Figure 7.6-2 Settings for Interval Timer Function (Timer 2)
204
Figure 7.6-3 Operation of Interval Timer Function (Timer 1) in 8-Bit Mode
205
Figure 7.6-4 Settings for Interval Timer Function (in 16-Bit Mode)
205
Operation of Counter Function
206
Figure 7.7-1 Settings for Counter Function (in 8-Bit Mode)
206
Figure 7.7-2 Settings for Counter Function (in 16-Bit Mode)
207
Figure 7.7-3 Operation of Counter Functions in 16-Bit Mode
208
Operation of Square Wave Output Initialization Function
209
Figure 7.8-1 Initialization Equivalent Circuit for Square Wave Output
209
Table 7.8-1 Square Wave Output Initialization Procedure (T1CR Register)
209
Figure 7.8-2 Initial Setup Operation of the Square Wave Output
210
Stop and Restart Operations of 8/16-Bit Timer/Counter
211
Table 7.9-1 Stop and Restart of Timer
211
States in each Mode During 8/16-Bit Timer/Counter Operation
212
Figure 7.10-1 Counter Operation During Subclock or Standby Modes and Operation Halt
213
7.11 Notes on Using 8/16-Bit Timer/Counter
214
Figure 7.11-1 Operation When Timer Stop Bit Is Used
214
Figure 7.11-2 Error on Starting Counter Operation
215
7.12 Program Examples for 8/16-Bit Timer/Counter
216
Chapter 8 8-Bit Serial I/O
220
Overview of 8-Bit Serial I/O
221
Table 8.1-1 Shift Clock Cycle and Transfer Speed
221
Structare of 8-Bit Serial I/O
222
Figure 8.2-1 Block Diagram of 8-Bit Serial I/O
222
8-Bit Serial I/O Pins
224
Figure 8.3-1 Block Diagram of 8-Bit Serial I/O Pins
225
8-Bit Serial I/O Registers
226
Figure 8.4-1 8-Bit Serial I/O-1 Registers
226
Figure 8.4-2 Serial Mode Register (SMR)
227
Serial Mode Register (SMR)
227
Table 8.4-1 Serial Mode Register (SMR) Bits
228
Figure 8.4-3 Serial Data Register (SDR)
230
Serial Data Register (SDR)
230
8-Bit Serial I/O Interrupts
231
Table 8.5-1 Register and Vector Table for 8-Bit Serial I/O Interrupts
231
Operation of Serial Output
232
Figure 8.6-1 Serial Output Settings (When Using Internal Shift Clock)
232
Figure 8.6-2 Serial Output Settings (When Using External Shift Clock)
232
Figure 8.6-3 8-Bit Serial Output Operation
233
Operation of Serial Input
234
Figure 8.7-1 Serial Input Settings (When Using Internal Shift Clock)
234
Figure 8.7-2 Serial Input Settings (When Using External Shift Clock)
234
Figure 8.7-3 8-Bit Serial Input Operation
235
States in each Mode During 8-Bit Serial I/O Operation
236
Figure 8.8-1 Operation in Sleep Mode (Internal Shift Clock)
236
Figure 8.8-2 Operation in Stop or Watch Mode (Internal Shift Clock)
236
Figure 8.8-3 Operation During Halt (Internal Shift Clock)
237
Figure 8.8-4 Operation in Sleep Mode (External Shift Clock)
237
Figure 8.8-5 Operation in Stop or Watch Mode (External Shift Clock)
238
Figure 8.8-6 Operation During Halt (External Shift Clock)
238
Notes on Using 8-Bit Serial I/O
239
Figure 8.9-1 Idle State of Shift Clock
239
8.10 Connection Example for 8-Bit Serial I/O
240
Figure 8.10-1 Connection Example for 8-Bit Serial I/O (Interface between Two Mb89120/120As)
240
Figure 8.10-2 Bidirectional Serial I/O Operation
241
8.11 Program Examples for 8-Bit Serial I/O
242
Chapter 9 Buzzer Output
246
Overview of Buzzer Output
247
Table 9.1-1 Output Frequency
247
Structure of Buzzer Output
249
Figure 9.2-1 Block Diagram of Buzzer Output
249
Buzzer Output Pin
250
Figure 9.3-1 Block Diagram of P37/BZ/(RCO) Pin
250
Buzzer Output Register
251
Figure 9.4-1 Buzzer Output Register
251
Buzzer Register (BZCR)
252
Figure 9.4-2 Buzzer Register (BZCR)
252
Table 9.4-1 Buzzer Register (BZCR) Bits
252
Program Example for Buzzer Output
254
Chapter 10 External Interrupt Circuit 1 (Edge)
256
Overview of External Interrupt Circuit 1 (Edge)
257
Structure of External Interrupt Circuit 1
258
Figure 10.2-1 Block Diagram of External Interrupt Circuit 1
258
10.3 External Interrupt Circuit 1 Pins
260
Table 10.3-1 External Interrupt Circuit 1 Pins
260
Figure 10.3-1 Block Diagram of External Interrupt Circuit 1 Pins
261
10.4 External Interrupt Circuit 1 Registers
262
Figure 10.4-1 External Interrupt Circuit Registers
262
External Interrupt 1 Control Register 1 (EIC1)
263
Figure 10.4-2 External Interrupt 1 Control Register 1 (EIC1)
263
Table 10.4-1 External Interrupt 1 Control Register 1 (EIC1) Bits
264
External Interrupt 1 Control Register 2 (EIC2)
265
Figure 10.4-3 External Interrupt 1 Control Register 2 (EIC2)
265
Table 10.4-2 External Interrupt 1 Control Register 2 (EIC2) Bits
265
10.5 External Interrupt Circuit 1 Interrupts
267
Table 10.5-1 Register and Vector Table for External Interrupt Circuit 1 Interrupts
267
Operation of External Interrupt Circuit 1
268
Figure 10.6-1 External Interrupt Circuit 1 Settings
268
Figure 10.6-2 External Interrupt (INT0) Operation
269
Program Example for External Interrupt Circuit 1
270
Chapter 11 External Interrupt Circuit 2 (Level)
272
Overview of External Interrupt Circuit 2 (Level)
273
Structure of External Interrupt Circuit 2
274
Figure 11.2-1 Block Diagram of External Interrupt Circuit 2
274
11.3 External Interrupt Circuit 2 Pins
276
Table 11.3-1 Terminals Related to External Interrupt Circuit 2 Pins
276
Figure 11.3-1 Block Diagram of External Interrupt Circuit 2 Pins
277
Table 11.3-2 Correspondence between Interrupt Enable Bits and External Interrupt Pins
277
11.4 External Interrupt Circuit 2 Registers
278
Figure 11.4-1 External Interrupt Circuit 2 Registers
278
External Interrupt 2 Control Register (EIC2)
279
Figure 11.4-2 External Interrupt Circuit 2 Control Register(EIE2)
279
Table 11.4-1 Correspondence between External Interrupt 2 Control Register (EIE2) Bits and External Interrupt Pins
279
Table 11.4-2 Functions of External Interrupt 2 Control Register (EIE2) Bits
280
External Interrupt 2 Flag Register (EIF2)
281
Figure 11.4-3 External Interrupt 2 Flag Register (EIF2)
281
Table 11.4-3 Functions of External Interrupt 2 Flag Register (EIF2) Bits
281
11.5 External Interrupt Circuit 2 Interrupts
282
Table 11.5-1 Register and Vector Table for External Interrupt Circuit 2 Interrupts
282
Operation of External Interrupt Circuit 2
283
Figure 11.6-1 External Interrupt Circuit 2 Settings
283
Figure 11.6-2 Operation of External Interrupt Circuit 2 (INT20)
284
Program Example for External Interrupt Circuit 2
285
Chapter 12 Watch Prescaler
288
12.1 Overview of Watch Prescaler
289
Table 12.1-1 Watch Prescaler Interval Time
289
Table 12.1-2 Clock Signals Supplied from Watch Prescaler
290
12.2 Structure of Watch Prescaler
291
Figure 12.2-1 Block Diagram of Watch Prescaler
291
Watch Prescaler Control Register (WPCR)
293
Figure 12.3-1 Watch Prescaler Control Register (WPCR)
293
Table 12.3-1 Functions of Watch Prescaler Control Register (WPCR) Bits
294
12.4 Watch Prescaler Interrupts
295
Table 12.4-1 Register and Vector Table for Watch Prescaler Interrupt
295
12.5 Operation of Watch Prescaler
296
Figure 12.5-1 Interval Timer Function Settings
296
Figure 12.5-2 Watch Prescaler Operation
297
12.6 Notes on Using Watch Prescaler
298
Figure 12.6-1 Effect of Clearing Watch Prescaler on Buzzer Output
299
12.7 Program Example for Watch Prescaler
300
Chapter 13 Remote-Control Transmission Frequency Generator
302
Overview of Remote-Control Transmission Frequency Generator
303
Table 13.1-1 Output Cycle and Variable "H" Width Ranges
303
Table 13.1-2 Resolutions and Output Cycles of 6-Bit PPG
305
Table 13.1-3 Resolutions and Output Cycles of 6-Bit PPG
306
Structure of Remote-Control Transmission Frequency Generator
308
Figure 13.2-1 Block Diagram of Remote-Control Transmission Frequency Generator
308
13.3 Remote-Control Transmission Frequency Generator Pin
310
Figure 13.3-1 Block Diagram of Remote-Control Transmission Frequency Generator Pin(P37/BZ/RCO)
310
Remote-Control Transmission Frequency Generator Registers
311
Figure 13.4-1 Remote-Control Transmission Frequency Generator Registers
311
Figure 13.4-2 Remote-Control Transmission Frequency Control Register 1 (RCR1)
312
Remote-Control Transmission Frequency Control Register 1 (RCR1)
312
Table 13.4-1 Functions of Remote-Control Transmission Frequency Control Register 1 (RCR1) Bits
312
Figure 13.4-3 Remote-Control Transmission Frequency Control Register 2 (RCR2)
314
Remote-Control Transmission Frequency Control Register 2 (RCR2)
314
Table 13.4-2 Functions of Remote-Control Transmission Frequency Control Register 2 (RCR2) Bits
314
Operation of Remote-Control Transmission Frequency Generator
316
Figure 13.5-1 Settings for Remote-Control Transmission Frequency Generator
316
Figure 13.5-2 Operation of Remote-Control Transmission Frequency Generator
317
Notes on Using Remote-Control Transmission Frequency Generator
318
Figure 13.6-1 Changing Set Values During Operation of Remote-Control Transmission Frequency Generator
319
Figure 13.6-2 Remote-Control Output Function
319
Figure 13.6-3 Error on Starting Counter Operation
320
Program Example for Remote-Control Transmission Frequency Generator
321
Chapter 14 Peripheral Control Clock Output
322
14.1 Overview of Peripheral Control Clock Output
323
Table 14.1-1 Peripheral Control Clock Output Frequencies
323
14.2 Structure of Peripheral Control Clock Output
324
Figure 14.2-1 Block Diagram of Peripheral Control Clock Output
324
14.3 Peripheral Control Clock Output Pin
325
Figure 14.3-1 Block Diagram of Peripheral Control Clock Output Pin
325
Figure 14.3-2 Peripheral Control Clock Register (SCGC)
326
Peripheral Control Clock Register (SCGC)
326
Table 14.3-1 Functions of Peripheral Control Clock Register (SCGC) Bits
326
14.4 Program Example for Peripheral Control Clock Output
328
Appendix
330
APPENDIX A I/O Map
331
Table A-1 I/O Map
331
APPENDIX B Overview of Instructions
334
Figure B-1 Instruction Code and Instruction Map
334
Table B-1 Instruction List Symbols
334
Addressing
336
Figure B.1-1 Direct Addressing
336
Figure B.1-2 Extended Addressing
336
Figure B.1-3 Bit Direct Addressing
337
Figure B.1-4 Index Addressing
337
Figure B.1-5 Pointer Addressing
337
Figure B.1-6 General-Purpose Register Addressing
338
Figure B.1-7 Immediate Addressing
338
Table B.1-1 Vector Table Addresses Corresponding to "Vct
338
Figure B.1-10 Inherent Addressing
339
Figure B.2-1 JMP @A
340
Figure B.2-2 MOVW A, PC
340
Special Instructions
340
Figure B.2-3 MULU a
341
Figure B.2-4 DIVU a
341
Figure B.2-5 XCHW A,PC
342
Figure B.2-6 Example Using XCHW A,PC
342
Figure B.2-7 Execution Example of CALLV #3
343
Bit Manipulation Instructions (SETB, CLRB)
344
Figure B.1-8 Vector Addressing
339
Figure B.1-9 Relative Addressing
339
Table B.3-1 Bus Operation for Bit Manipulation Instructions
344
F 2 MC-8L Instructions
345
Table B.4-1 Transfer Instructions
345
Table B.4-2 Arithmetic Operation Instructions
346
Table B.4-3 Branch Instructions
348
Table B.4-4 Other Instructions
349
Table B.4-5 Instruction List Columns
349
Instruction Map
351
Table B.5-1 F2MC-8L Instruction Map
351
APPENDIX C Mask Options
353
Table C-1 Mask Options List
353
Table C-2 Standard Options
354
Table C-3 Ordering Information
354
APPENDIX D Programming PROM
355
Programming One-Time PROM
356
Table D.1-1 ROM Programmer Adapter and Recommended ROM Programmers
356
Figure D.1-1 Memory Map in PROM Mode (MB89P131)
357
Figure D.1-2 Memory Map in PROM Mode (MB89P133A)
357
Figure D.1-3 Memory Map in PROM Mode (MB89P135A)
358
Table D.1-2 PROM Option Bit Map
359
Figure D.1-4 Screening Flowchart
360
Figure D.2-1 Memory Map of Piggyback/Evaluation Device
361
Programming EPROM with Piggyback/Evaluation Device
361
Table D.2-1 Programming Socket Adapter
361
APPENDIX Emb89120 Series Pin States
363
Index
366
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