Fujitsu MB91350A Series Manuals

Manuals and User Guides for Fujitsu MB91350A Series. We have 1 Fujitsu MB91350A Series manual available for free PDF download: Hardware Manual

Fujitsu MB91350A Series Hardware Manual (664 pages)

Brand: Fujitsu | Category: Microcontrollers | Size: 3.88 MB

Table of Contents
9
Chapter 1 Overview

19
- Features
  20
- Block Diagram
  25
- Package Dimensions
  27
- Pin Layout
  29
- List of Pin Functions
  31
- Input-Output Circuit Forms
  45
Chapter 2 Handling the Device

49
- Precautions on Handling the Device
  50
- Precautions on Using the Little-Endian Area
  55
  - C Compiler (Fcc911)
    56
  - Assembler (Fasm911)
    59
  - Linker (Flnk911)
    60
  - Debuggers (Sim911, Eml911, and Mon911)
    61
Chapter 3 Cpu and Control Units

63
- Memory Space
  64
- Internal Architecture
  67
  - Internal Architecture
    68
  - Overview of Instructions
    71
- Programming Model
  73
  - General-Purpose Registers
    74
  - Dedicated Registers
    75
- Data Configuration
  82
- Memory Map
  84
- Branch Instructions
  85
  - Operations with a Delay Slot
    86
  - Operation Without Delay Slot
    89
- EIT (Exception, Interrupt, and Trap)
  90
  - EIT Interrupt Levels
    91
  - ICR (Interrupt Control Register)
    93
  - SSP (System Stack Pointer)
    95
  - Interrupt Stack
    96
  - TBR (Table Base Register)
    97
  - EIT Vector Table
    98
  - Multiple EIT Processing
    102
  - Operations
    104
- Operating Modes
  108
  - Bus Modes
    109
  - Mode Settings
    110
- Reset (Device Initialization)
  112
  - Reset Levels
    113
  - Reset Sources
    114
  - Reset Sequence
    116
  - Oscillation Stabilization Wait Time
    117
  - Reset Operation Modes
    120
- Clock Generation Control
  122
  - PLL Controls
    123
  - Oscillation Stabilization Wait Time and PLL Lock Wait Time
    124
  - Clock Distribution
    126
  - Clock Division
    128
  - Block Diagram of Clock Generation Controller
    129
  - Register of Clock Generation Controller
    130
  - Peripheral Circuits of Clock Controller
    147
- Device State Control
  151
  - Device States and State Transitions
    152
  - Low-Power Consumption Modes
    156
- Watch Timer
  161
- Main Clock Oscillation Stabilization Wait Timer
  167
- Peripheral Stop Control
  173
Chapter 4 External Bus Interface

179
- Overview of the External Bus Interface
  180
- External Bus Interface Registers
  185
- Setting Example of the Chip Select Area
  204
- Byte Ordering (Endian) and Bus Access
  206
  - Relationship between Data Bus Widths and Control Signals
    207
  - Big Endian Bus Access
    208
  - Little Endian Bus Access
    215
  - External Access
    219
- Ordinary Bus Interface
  223
- Address/Data Multiplex Interface
  233
- Prefetch Operation
  236
- DMA Access Operation
  240
- Bus Arbitration
  246
- Procedure for Setting a Register
  248
Chapter 5 I/O Port

249
- Overview of the I/O Port
  250
- I/O Port Registers
  252
CHAPTER 6 8/16-Bit Up/Down Counters/Timer and U-Timers

263
- 8/16-Bit Up/Down Counters/Timers
  264
- U-Timer
  286
  - Overview of the U-TIMER
    287
  - U-TIMER Registers
    288
  - Operation of the U-TIMER
    293
Chapter 7 16-Bit Free-Running Timer and 16-Bit Reload Timer

296
- 16-Bit Free-Running Timer
  296
- 16-Bit Reload Timer
  304
Chapter 8 Programmable Pulse Generator (Ppg) Timer

315
Chapter 9 Interrupt Controller

341
Chapter 10 External Interrupt and Nmi Controller

359
Chapter 11 Realos-Related Hardware

369
- Delayed Interrupt Module
  370
- Bit Search Module
  374
Chapter 12 A/D Converter

381
- Overview of the A/D Converter
  382
- A/D Converter Registers
  384
- Operation of the A/D Converter
  394
Chapter 13 8-Bit D/A Converter

394
Chapter 14 Uart, Serial I/O Interface (Sio), Input Capture Module, and Output Compare Module

403
- Uart
  404
  - Features of the UART
    405
  - UART Registers
    408
  - Operation of the UART
    417
  - Example of Using the UART
    425
- Serial I/O Interface (SIO)
  428
- Input Capture Module
  443
  - Overview of the Input Capture Module
    444
  - Input Capture Module Registers
    446
  - Input Capture Operation
    448
- Output Compare
  449
Chapter 15 I 2 C Interface

457
- Overview of the I 2 C Interface
  458
- C Interface Registers
  462
  - Bus Status Register (IBSR)
    463
  - Bus Control Register (IBCR)
    466
  - Clock Control Register (ICCR)
    473
  - 10-Bit Slave Address Register (ITBA)
    475
  - 10-Bit Slave Address Mask Register (ITMK)
    476
  - 7-Bit Slave Address Register (ISBA)
    478
  - 7-Bit Slave Address Mask Register (ISMK)
    479
  - Data Register (IDAR)
    480
  - Clock Disable Register (IDBL)
    481
- Explanation of I 2 C Interface Operation
  482
- Operation Flowcharts
  486
Chapter 16 Dma Controller (Dmac)

489
- Overview
  490
- Detailed Explanation of Registers
  493
- Explanation of Operation
  510
  - Overview of Operation
    511
  - Setting a Transfer Request
    514
  - Transfer Sequence
    515
  - General Aspects of DMA Transfer
    519
  - Addressing Mode
    521
  - Data Types
    522
  - Transfer Count Control
    523
  - CPU Control
    524
  - Hold Arbitration
    525
  - Operation from Starting to End/Stopping
    526
  - Transfer Request Acceptance and Transfer
    527
  - Clearing Peripheral Interrupts by DMA
    528
  - Temporary Stopping
    529
  - Operation End/Stopping
    530
  - Stopping Due to an Error
    531
  - DMAC Interrupt Control
    532
  - DMA Transfer During Sleep
    533
  - Channel Selection and Control
    534
  - Supplement on External Pin and Internal Operation Timing
    536
- Operation Flowcharts
  540
- Data Path
  543
- DMA External Interface
  547
Chapter 17 Flash Memory

551
- Outline of Flash Memory
  552
- Flash Memory Registers
  557
  - Flash Control/Status Register (FLCR) (CPU Mode)
    558
  - Flash Memory Wait Register (FLWC)
    561
- Explanation of Flash Memory Operation
  563
- Automatic Algorithm of Flash Memory
  565
  - Command Sequence
    566
  - Checking the Automatic Algorithm Operating Status
    570
- Writing to and Erasing Flash Memory
  575
  - Read/Reset Status
    576
  - Data Writing
    577
  - Data Erasure (Chip Erasure)
    579
  - Data Erasure (Sector Erasure)
    580
  - Temporary Sector Erase Stop
    582
  - Sector Erase Restart
    583
Chapter 18 Mb91F355A/F353A/F356B/F357B Serial Programming Connection

586
Chapter 19 Data Internal Ram/Instruction Internal Ram

594
- Overview
  594
- Explanation of Registers
  595
- Explanation of Operation
  597
Appendix

599
- APPENDIX A I/O Map
  
  600
- APPENDIX B Interrupt Vector
  
  612
- APPENDIX C Pin States in each CPU State
  
  615
- APPENDIX D Instruction Lists
  
  621
Index

637

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Fujitsu MB91350A Series Manuals

Fujitsu MB91350A Series Hardware Manual (664 pages)

Table of Contents

Chapter 1 Overview

Chapter 2 Handling the Device

Chapter 3 Cpu and Control Units

Chapter 4 External Bus Interface

Chapter 5 I/O Port

CHAPTER 6 8/16-Bit Up/Down Counters/Timer and U-Timers

Chapter 7 16-Bit Free-Running Timer and 16-Bit Reload Timer

Chapter 8 Programmable Pulse Generator (Ppg) Timer

Chapter 9 Interrupt Controller

Chapter 10 External Interrupt and Nmi Controller

Chapter 11 Realos-Related Hardware

Chapter 12 A/D Converter

Chapter 13 8-Bit D/A Converter

Chapter 14 Uart, Serial I/O Interface (Sio), Input Capture Module, and Output Compare Module

Chapter 15 I 2 C Interface

Chapter 16 Dma Controller (Dmac)

Chapter 17 Flash Memory

Chapter 18 Mb91F355A/F353A/F356B/F357B Serial Programming Connection

Chapter 19 Data Internal Ram/Instruction Internal Ram

Appendix

APPENDIX A I/O Map

APPENDIX B Interrupt Vector

APPENDIX C Pin States in each CPU State

APPENDIX D Instruction Lists

Index

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