Hitachi H8/3021 Manuals

Manuals and User Guides for Hitachi H8/3021. We have 1 Hitachi H8/3021 manual available for free PDF download: Hardware Manual

Hitachi H8/3021 Hardware Manual (674 pages)

H8/3022 Series Hitachi Single-Chip Microcomputer

Brand: Hitachi | Category: Computer Hardware | Size: 2.08 MB

Table of Contents
4
Section 1 Overview

15
- Overview
  15
- Block Diagram
  19
- Pin Description
  20
  - Pin Arrangement
    20
  - Pin Functions
    21
- Pin Functions
  25
Cpu

29
- Overview
  29
  - Features
    29
  - Differences from H8/300 CPU
    30
- CPU Operating Modes
  31
- Address Space
  32
- Register Configuration
  33
  - Overview
    33
  - General Registers
    34
  - Control Registers
    35
  - Initial CPU Register Values
    36
- Data Formats
  37
  - General Register Data Formats
    37
  - Memory Data Formats
    38
- Instruction Set
  40
- Addressing Modes and Effective Address Calculation
  55
  - Addressing Modes
    55
  - Effective Address Calculation
    57
- Processing States
  61
  - Overview
    61
  - Program Execution State
    62
  - Exception-Handling State
    62
  - Exception-Handling Sequences
    64
  - Reset State
    65
  - Power-Down State
    65
- Basic Operational Timing
  66
MCU Operating Modes

69
- Overview
  69
  - Operating Mode Selection
    69
  - Register Configuration
    70
- Mode Control Register (MDCR)
  71
- System Control Register (SYSCR)
  72
- Operating Mode Descriptions
  74
  - Mode 1
    74
  - Mode 3
    74
- Pin Functions in each Operating Mode
  75
- Memory Map in each Operating Mode
  75
Exception Handling

82
- Overview
  82
- Reset
  85
  - Overview
    85
  - Reset Sequence
    85
  - Interrupts after Reset
    87
- Interrupts
  87
- Trap Instruction
  88
- Stack Status after Exception Handling
  88
- Notes on Stack Usage
  89
Interrupt Controller

90
- Overview
  90
  - Features
    90
  - Block Diagram
    91
  - Pin Configuration
    92
  - Register Configuration
    92
- Register Descriptions
  93
- Interrupt Sources
  103
  - External Interrupts
    103
  - Internal Interrupts
    104
  - Interrupt Vector Table
    104
- Interrupt Operation
  107
  - Interrupt Handling Process
    107
  - Interrupt Sequence
    112
  - Interrupt Response Time
    113
- Usage Notes
  114
Bus Controller

118
- Overview
  118
  - Features
    118
  - Block Diagram
    119
  - Pin Configuration
    120
  - Register Configuration
    120
- Register Descriptions
  121
- Operation
  126
  - Area Division
    126
  - Memory Map
    126
  - Bus Control Signal Timing
    128
  - Wait Modes
    130
  - Interconnections with Memory (Example)
    136
- Usage Notes
  138
  - Register Write Timing
    138
  - Precautions on Setting ASTCR and ABWCR
    138
I/O Ports

139
- Overview
  139
- Port 1
  143
  - Overview
    143
  - Register Descriptions
    143
  - Pin Functions in each Mode
    150
- Port 2
  164
  - Overview
    167
  - Overview
    168
  - Overview
    171
  - Overview
    175
  - Register Descriptions
    176
  - Pin Functions
    182
- Port B
  185
  - Pin Functions
    189
16-Bit Integrated Timer Unit (ITU)

193
- Overview
  193
  - Features
    193
  - Block Diagrams
    196
  - Pin Configuration
    201
  - Register Configuration
    203
  - Timer Start Register (TSTR)
    203
  - Timer Synchro Register (TSNC)
    207
  - Timer Mode Register (TMDR)
    209
  - Timer Function Control Register (TFCR)
    212
  - Timer Output Master Enable Register (TOER)
    214
  - Timer Output Control Register (TOCR)
    217
  - Timer Counters (TCNT)
    218
  - General Registers (GRA, GRB)
    219
  - Buffer Registers (BRA, BRB)
    220
  - Timer Control Registers (TCR)
    221
  - Timer I/O Control Register (TIOR)
    224
  - Timer Status Register (TSR)
    226
  - Timer Interrupt Enable Register (TIER)
    228
- CPU Interface
  230
  - 16-Bit Accessible Registers
    230
  - 8-Bit Accessible Registers
    232
- Operation
  233
  - Overview
    233
  - Basic Functions
    234
  - Synchronization
    244
  - PWM Mode
    246
  - Reset-Synchronized PWM Mode
    250
  - Complementary PWM Mode
    253
  - Phase Counting Mode
    263
  - Buffering
    265
  - ITU Output Timing
    272
- Interrupts
  274
  - Setting of Status Flags
    274
  - Clearing of Status Flags
    276
  - Interrupt Sources
    277
- Usage Notes
  278
Programmable Timing Pattern Controller

293
- Overview
  293
  - Features
    293
  - Block Diagram
    294
  - Pin Configuration
    295
  - Register Configuration
    296
- Register Descriptions
  297
  - Port a Data Direction Register (PADDR)
    297
  - Port a Data Register (PADR)
    297
  - Port B Data Direction Register (PBDDR)
    298
  - Port B Data Register (PBDR)
    298
  - Next Data Register a (NDRA)
    299
  - Next Data Register B (NDRB)
    301
  - Next Data Enable Register a (NDERA)
    303
  - Next Data Enable Register B (NDERB)
    304
  - TPC Output Control Register (TPCR)
    305
  - TPC Output Mode Register (TPMR)
    308
- Operation
  310
  - Overview
    310
  - Output Timing
    311
  - Normal TPC Output
    313
  - Non-Overlapping TPC Output
    314
- Usage Notes
  317
  - Operation of TPC Output Pins
    317
  - Note on Non-Overlapping Output
    317
Section 10 Watchdog Timer

319
- Overview
  319
  - Features
    319
  - Block Diagram
    320
  - Pin Configuration
    320
  - Register Configuration
    321
  - Timer Counter (TCNT)
    321
  - Timer Control/Status Register (TCSR)
    323
  - Reset Control/Status Register (RSTCSR)
    325
  - Notes on Register Access
    327
- Operation
  329
- Interrupts
  333
- Usage Notes
  333
Section 11 Serial Communication Interface

334
- Overview
  334
  - Features
    334
  - Block Diagram
    336
  - Pin Configuration
    337
  - Register Configuration
    337
- Register Descriptions
  338
  - Receive Shift Register (RSR)
    338
  - Receive Data Register (RDR)
    338
  - Transmit Shift Register (TSR)
    339
  - Transmit Data Register (TDR)
    339
  - Serial Mode Register (SMR)
    340
  - Serial Control Register (SCR)
    344
  - Serial Status Register (SSR)
    348
  - Bit Rate Register (BRR)
    352
- Operation
  361
  - Overview
    361
  - Operation in Asynchronous Mode
    363
  - Multiprocessor Communication
    372
  - Synchronous Operation
    379
- SCI Interrupts
  388
- Usage Notes
  389
Section 12 Smart Card Interface

394
- Overview
  394
  - Features
    394
  - Block Diagram
    395
  - Pin Configuration
    396
  - Register Configuration
    396
- Register Descriptions
  397
  - Smart Card Mode Register (SCMR)
    397
  - Serial Status Register (SSR)
    399
- Operation
  401
  - Overview
    401
  - Pin Connections
    401
  - Data Format
    403
  - Register Settings
    405
  - Clock
    407
  - Data Transfer Operations
    409
- Usage Note
  415
Section 13 A/D Converter

418
- Overview
  418
  - Features
    418
  - Block Diagram
    419
  - Pin Configuration
    420
  - Register Configuration
    421
- Register Descriptions
  422
- CPU Interface
  427
- Operation
  428
  - Single Mode (SCAN = 0)
    428
  - Scan Mode (SCAN = 1)
    430
  - Input Sampling and A/D Conversion Time
    432
  - External Trigger Input Timing
    433
- Interrupts
  434
- Usage Notes
  434
Section 14 RAM

440
- Overview
  440
  - Block Diagram
    441
  - Register Configuration
    441
- System Control Register (SYSCR)
  442
- Operation
  443
Section 15 ROM

444
- Features
  444
- Overview
  445
  - Block Diagram
    445
  - Mode Transitions
    446
  - On-Board Programming Modes
    447
  - Flash Memory Emulation in RAM
    449
  - Differences between Boot Mode and User Program Mode
    450
  - Block Configuration
    451
- Pin Configuration
  451
- Register Configuration
  452
- Register Descriptions
  452
- On-Board Programming Modes
  461
  - Boot Mode
    462
  - User Program Mode
    468
- Programming/Erasing Flash Memory
  469
  - Program Mode
    470
  - Program-Verify Mode
    471
  - Notes on Program/Program-Verify Procedure
    471
  - Erase Mode
    476
  - Erase-Verify Mode
    476
- Protection
  478
  - Hardware Protection
    478
  - Software Protection
    479
  - Error Protection
    480
  - NMI Input Disable Conditions
    482
- Flash Memory Emulation in RAM
  483
- Flash Memory PROM Mode
  485
  - Socket Adapters and Memory Map
    485
  - Notes on Use of PROM Mode
    486
- Notes on Flash Memory Programming/Erasing
  487
- Overview of Mask ROM
  493
  - Block Diagram
    493
- Notes on Ordering Mask ROM Version Chips
  494
- Notes When Converting the F-ZTAT Application Software to the Mask-ROM Versions
  495
Section 16 Clock Pulse Generator

496
- Overview
  496
  - Block Diagram
    497
- Oscillator Circuit
  498
  - Connecting a Crystal Resonator
    498
  - External Clock Input
    500
- Duty Adjustment Circuit
  503
- Prescalers
  503
- Frequency Divider
  503
  - Register Configuration
    503
  - Division Control Register (DIVCR)
    504
  - Usage Notes
    504
Section 17 Power-Down State

505
- Overview
  505
- Register Configuration
  507
  - System Control Register (SYSCR)
    507
  - Module Standby Control Register (MSTCR)
    509
- Sleep Mode
  511
  - Transition to Sleep Mode
    511
  - Exit from Sleep Mode
    511
- Software Standby Mode
  512
- Module Standby Function
  516
  - Module Standby Timing
    516
  - Read/Write in Module Standby
    516
  - Usage Notes
    516
- System Clock Output Disabling Function
  517
Section 18 Electrical Characteristics

518
- Electrical Characteristics of Masked ROM Version
  518
  - Absolute Maximum Ratings
    518
  - DC Characteristics
    519
  - AC Characteristics
    523
  - A/D Conversion Characteristics
    528
- Electrical Characteristics of Flash Memory Version
  529
  - Absolute Maximum Ratings
    529
  - DC Characteristics
    530
  - AC Characteristics
    534
  - A/D Conversion Characteristics
    539
  - Flash Memory Characteristics
    540
- Operational Timing
  541
  - Bus Timing
    541
  - Control Signal Timing
    545
  - Clock Timing
    547
  - TPC and I/O Port Timing
    547
  - ITU Timing
    548
  - SCI Input/Output Timing
    549
Appendix A Instruction Set

550
- Instruction List
  550
  - Data Transfer Instructions
    552
  - Arithmetic Instructions
    554
  - Bit Manipulation Instructions
    559
- Number of States Required for Execution
  568
Appendix B Internal I/O Register Field

578
- Addresses
  578
- Function
  585
Appendix C I/O Block Diagrams

644
- Port 1 Block Diagram
  644
- Port 2 Block Diagram
  645
- Port 3 Block Diagram
  646
- Port 5 Block Diagram
  647
- Port 6 Block Diagrams
  648
- Port 7 Block Diagram
  650
- Port 8 Block Diagrams
  651
- Port 9 Block Diagrams
  653
- Port a Block Diagrams
  657
- Port B Block Diagrams
  660
Appendix D Pin States

663
- Port States in each Mode
  663
- Pin States at Reset
  665
Appendix E Timing of Transition to and Recovery from Hardware Standby Mode

668
Appendix F Product Code Lineup

669
Appendix G Package Dimensions

670
Appendix H Comparison of H8/300H Series Product Specifications

672
- Differences between H8/3039F and H8/3022F
  672

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Hitachi H8/3021 Manuals

Hitachi H8/3021 Hardware Manual (674 pages)

Table of Contents

Section 1 Overview

Cpu

MCU Operating Modes

Exception Handling

Interrupt Controller

Bus Controller

I/O Ports

16-Bit Integrated Timer Unit (ITU)

Programmable Timing Pattern Controller

Section 10 Watchdog Timer

Section 11 Serial Communication Interface

Section 12 Smart Card Interface

Section 13 A/D Converter

Section 14 RAM

Section 15 ROM

Section 16 Clock Pulse Generator

Section 17 Power-Down State

Section 18 Electrical Characteristics

Appendix A Instruction Set

Appendix B Internal I/O Register Field

Appendix C I/O Block Diagrams

Appendix D Pin States

Appendix E Timing of Transition to and Recovery from Hardware Standby Mode

Appendix F Product Code Lineup

Appendix G Package Dimensions

Appendix H Comparison of H8/300H Series Product Specifications

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