Hitachi H8/3044 Manuals

Manuals and User Guides for Hitachi H8/3044. We have 1 Hitachi H8/3044 manual available for free PDF download: Hardware Manual

Hitachi H8/3044 Hardware Manual

Hitachi H8/3044 Hardware Manual (867 pages)

Single-Chip Microcomputer

Brand: Hitachi | Category: Computer Hardware | Size: 2.67 MB

Table of Contents

Table of Contents
3
Overview

16
- Block Diagram
  20
- Pin Description
  21
  - Pin Arrangement
    21
  - Pin Assignments in each Mode
    22
  - Pin Functions
    25
Cpu

30
- Overview
  30
  - Features
    30
  - Differences from H8/300 CPU
    31
- CPU Operating Modes
  32
- Address Space
  33
- Register Configuration
  34
  - Overview
    34
  - General Registers
    35
  - Control Registers
    36
  - Initial CPU Register Values
    37
- Data Formats
  38
  - General Register Data Formats
    38
  - Memory Data Formats
    40
- Instruction Set
  41
- Addressing Modes and Effective Address Calculation
  54
  - Addressing Modes
    54
  - Effective Address Calculation
    57
- Processing States
  61
  - Overview
    61
  - Program Execution State
    62
  - Exception-Handling State
    62
  - Exception-Handling Sequences
    64
  - Bus-Released State
    65
  - Reset State
    65
  - Power-Down State
    65
- Basic Operational Timing
  66
MCU Operating Modes

70
- Overview
  70
  - Operating Mode Selection
    70
  - Register Configuration
    71
- Mode Control Register (MDCR)
  72
- System Control Register (SYSCR)
  73
- Operating Mode Descriptions
  75
  - Mode 1
    75
  - Mode 2
    75
  - Mode 3
    75
  - Mode 4
    75
  - Mode 5
    75
  - Mode 6
    75
  - Mode 7
    76
- Pin Functions in each Operating Mode
  76
- Memory Map in each Operating Mode
  76
Exception Handling

85
- Overview
  85
- Reset
  87
  - Overview
    87
  - Reset Sequence
    87
  - Interrupts after Reset
    90
- Interrupts
  91
- Trap Instruction
  92
- Stack Status after Exception Handling
  93
- Notes on Stack Usage
  94
Interrupt Controller

95
- Overview
  95
  - Features
    95
  - Block Diagram
    96
  - Pin Configuration
    97
  - Register Configuration
    97
  - System Control Register (SYSCR)
    97
  - Interrupt Priority Registers a and B (IPRA, IPRB)
    99
  - IRQ Status Register (ISR)
    106
  - IRQ Enable Register (IER)
    107
  - IRQ Sense Control Register (ISCR)
    108
- Interrupt Sources
  109
  - External Interrupts
    109
  - Internal Interrupts
    110
  - Interrupt Vector Table
    110
- Interrupt Operation
  114
  - Interrupt Handling Process
    114
  - Interrupt Sequence
    119
  - Interrupt Response Time
    120
- Usage Notes
  121
Bus Controller

125
- Overview
  125
  - Features
    125
  - Block Diagram
    126
  - Input/Output Pins
    127
  - Register Configuration
    127
- Register Descriptions
  128
- Operation
  135
  - Area Division
    135
  - Chip Select Signals
    136
  - Data Bus
    138
  - Bus Control Signal Timing
    139
  - Wait Modes
    147
  - Interconnections with Memory (Example)
    153
  - Bus Arbiter Operation
    155
  - Connection to Dynamic RAM and Pseudo-Static RAM
    158
  - Register Write Timing
    158
  - BREQ Input Timing
    160
  - Transition to Software Standby Mode
    160
Refresh Controller

161
- Overview
  161
  - Features
    161
  - Block Diagram
    162
  - Input/Output Pins
    163
  - Register Configuration
    163
- Register Descriptions
  164
- Operation
  170
  - DRAM Refresh Control
    171
  - Pseudo-Static RAM Refresh Control
    186
  - Interval Timing
    191
- Interrupt Source
  197
- Usage Notes
  197
DMA Controller

199
- Overview
  199
  - Features
    199
  - Block Diagram
    200
  - Functional Overview
    201
  - Input/Output Pins
    202
  - Register Configuration
    202
- Register Descriptions (Short Address Mode)
  204
- Register Descriptions (Full Address Mode)
  210
  - Memory Address Registers (MAR)
    210
  - I/O Address Registers (IOAR)
    210
- Www.datasheet4U.com
  211
  - Execute Transfer Count Registers (ETCR)
    211
  - Data Transfer Control Registers (DTCR)
    213
- Operation
  219
  - Overview
    219
  - I/O Mode
    221
  - Idle Mode
    223
  - Repeat Mode
    226
  - Normal Mode
    229
  - Block Transfer Mode
    232
  - DMAC Activation
    237
  - DMAC Bus Cycle
    239
  - Multiple-Channel Operation
    245
  - External Bus Requests, Refresh Controller, and DMAC
    246
  - NMI Interrupts and DMAC
    247
  - Aborting a DMA Transfer
    248
  - Exiting Full Address Mode
    249
  - DMAC States in Reset State, Standby Modes, and Sleep Mode
    250
- Interrupts
  251
- Usage Notes
  252
I/O Ports

256
- Overview
  256
- Port 1
  259
  - Overview
    259
  - Register Descriptions
    269
- Port 2
  272
  - Overview
    272
  - Register Descriptions
    275
- Port 3
  275
- Port 4
  275
  - Overview
    278
- Port 7
  279
  - Overview
    280
- Port 8
  285
- Port 9
  285
- Port a
  289
  - Register Descriptions
    291
  - Pin Functions
    292
- Port B
  297
  - Register Descriptions
    299
  - Pin Functions
    301
16-Bit Integrated Timer Unit (ITU)

307
- Overview
  307
  - Features
    307
  - Block Diagrams
    310
  - Input/Output Pins
    315
  - Register Configuration
    316
- Register Descriptions
  319
  - Timer Start Register (TSTR)
    319
  - Timer Synchro Register (TSNC)
    320
  - Timer Mode Register (TMDR)
    322
  - Timer Function Control Register (TFCR)
    325
  - Timer Output Master Enable Register (TOER)
    327
  - Timer Output Control Register (TOCR)
    330
  - Timer Counters (TCNT)
    331
  - General Registers (GRA, GRB)
    332
  - Buffer Registers (BRA, BRB)
    333
  - Timer Control Registers (TCR)
    334
  - Timer I/O Control Register (TIOR)
    336
  - Timer Status Register (TSR)
    338
  - Timer Interrupt Enable Register (TIER)
    341
- CPU Interface
  343
  - 16-Bit Accessible Registers
    343
  - 8-Bit Accessible Registers
    345
- Operation
  347
  - Overview
    347
  - Basic Functions
    348
  - Complementary PWM Mode
    348
  - Phase Counting Mode
    377
  - Buffering
    379
  - ITU Output Timing
    386
- Interrupts
  388
- Usage Notes
  392
Programmable Timing Pattern Controller

407
- Overview
  407
  - Features
    407
  - Block Diagram
    408
  - TPC Pins
    409
  - Registers
    410
- Register Descriptions
  411
  - Port a Data Direction Register (PADDR)
    411
  - Port a Data Register (PADR)
    411
  - Port B Data Direction Register (PBDDR)
    412
  - Port B Data Register (PBDR)
    412
  - Next Data Register a (NDRA)
    413
  - Next Data Register B (NDRB)
    415
  - Next Data Enable Register a (NDERA)
    417
  - Next Data Enable Register B (NDERB)
    418
  - TPC Output Control Register (TPCR)
    419
  - TPC Output Mode Register (TPMR)
    422
- Operation
  424
  - Output Timing
    425
  - Normal TPC Output
    426
  - Non-Overlapping TPC Output
    428
  - TPC Output Triggering by Input Capture
    430
- Usage Notes
  431
  - Operation of TPC Output Pins
    431
  - Note on Non-Overlapping Output
    431
Watchdog Timer

433
- Overview
  433
  - Features
    433
  - Block Diagram
    434
  - Pin Configuration
    434
  - Register Configuration
    435
- Register Descriptions
  436
- Operation
  443
- Interrupts
  447
- Usage Notes
  447
Serial Communication Interface

448
- Overview
  448
  - Features
    448
  - Block Diagram
    450
  - Input/Output Pins
    451
  - Register Configuration
    451
- Register Descriptions
  452
  - Receive Shift Register (RSR)
    452
  - Receive Data Register (RDR)
    452
  - Transmit Shift Register (TSR)
    453
  - Transmit Data Register (TDR)
    453
  - Serial Mode Register (SMR)
    454
  - Serial Control Register (SCR)
    458
  - Serial Status Register (SSR)
    462
  - Bit Rate Register (BRR)
    466
- Operation
  475
  - Operation in Asynchronous Mode
    477
  - Multiprocessor Communication
    486
  - Synchronous Operation
    493
- SCI Interrupts
  502
- Usage Notes
  503
Smart Card Interface

507
- Overview
  507
  - Features
    507
  - Block Diagram
    508
  - Input/Output Pins
    509
  - Register Configuration
    509
- Register Descriptions
  510
  - Smart Card Mode Register (SCMR)
    510
  - Serial Status Register (SSR)
    511
  - Serial Mode Register (SMR)
    513
  - Serial Control Register (SCR)
    514
- Operation
  515
  - Overview
    515
  - Pin Connections
    515
  - Data Format
    516
  - Register Settings
    518
  - Clock
    520
  - Transmitting and Receiving Data
    522
- Usage Notes
  529
A/D Converter

533
- Overview
  533
  - Features
    533
  - Block Diagram
    534
  - Input Pins
    535
  - Register Configuration
    536
- Register Descriptions
  537
  - A/D Control/Status Register (ADCSR)
    538
  - A/D Control Register (ADCR)
    541
- CPU Interface
  542
- Operation
  543
  - Single Mode (SCAN = 0)
    543
  - Scan Mode (SCAN = 1)
    545
  - Input Sampling and A/D Conversion Time
    547
  - External Trigger Input Timing
    548
- Interrupts
  549
- Usage Notes
  549
D/A Converter

555
- Overview
  555
  - Features
    555
  - Block Diagram
    555
  - Input/Output Pins
    556
  - Register Configuration
    556
- Register Descriptions
  557
  - D/A Control Register (DACR)
    557
  - D/A Standby Control Register (DASTCR)
    559
- D/A Output Control
  561
- Usage Notes
  561
Ram

562
- Overview
  562
  - Block Diagram
    562
  - Register Configuration
    563
- System Control Register (SYSCR)
  564
- Operation
  565
Rom

566
- Overview
  566
  - Block Diagram
    567
- PROM Mode
  568
  - PROM Mode Setting
    568
  - Socket Adapter and Memory Map
    568
- PROM Programming
  571
  - Programming and Verification
    571
  - Programming Precautions
    576
  - Reliability of Programmed Data
    577
- Flash Memory Overview
  578
  - Flash Memory Operation
    578
  - Features
    579
  - Mode Programming and Flash Memory Address Space
    579
  - Block Diagram
    581
  - Input/Output Pins
    582
  - Register Configuration
    582
- Flash Memory Register Descriptions
  583
  - Erase Block Register 2
    587
  - RAM Control Register (RAMCR)
    589
- On-Board Programming Modes
  591
  - Boot Mode
    591
  - User Program Mode
    596
- Programming and Erasing Flash Memory
  598
  - Program Mode
    599
  - Program-Verify Mode
    599
  - Programming Flowchart and Sample Program
    600
  - Erase Mode
    602
  - Erase-Verify Mode
    603
  - Erasing Flowchart and Sample Program
    604
  - Prewrite-Verify Mode
    616
  - Protect Modes
    616
  - NMI Input Masking
    619
- Flash Memory Emulation by RAM
  620
- PROM Mode
  622
  - PROM Mode Setting
    622
  - Socket Adapter and Memory Map
    623
  - Operation in PROM Mode
    625
- Flash Memory Programming and Erasing Precautions
  633
Clock Pulse Generator

642
- Overview
  642
  - Block Diagram
    642
- Oscillator Circuit
  643
  - Connecting a Crystal Resonator
    643
  - External Clock Input
    645
- Duty Adjustment Circuit
  648
- Prescalers
  648
- Frequency Divider
  648
  - Register Configuration
    648
  - Division Control Register (DIVCR)
    648
  - Usage Notes
    649
Power-Down State

650
- Overview
  650
- Register Configuration
  652
  - System Control Register (SYSCR)
    652
  - Module Standby Control Register (MSTCR)
    654
- Sleep Mode
  656
  - Transition to Sleep Mode
    656
  - Exit from Sleep Mode
    656
- Software Standby Mode
  657
- Hardware Standby Mode
  660
- Module Standby Function
  661
  - Read/Write in Module Standby
    661
  - Usage Notes
    661
- System Clock Output Disabling Function
  662
Electrical Characteristics

663
- Absolute Maximum Ratings
  663
- Electrical Characteristics of Masked ROM and PROM Versions
  664
  - DC Characteristics
    664
  - AC Characteristics
    672
  - A/D Conversion Characteristics
    680
  - D/A Conversion Characteristics
    681
- Electrical Characteristics of Flash Memory Version
  682
  - DC Characteristics
    682
  - AC Characteristics
    691
  - A/D Conversion Characteristics
    697
  - D/A Conversion Characteristics
    698
  - Flash Memory Characteristics
    699
- Operational Timing
  700
  - Bus Timing
    700
  - Refresh Controller Bus Timing
    704
  - Control Signal Timing
    709
  - Clock Timing
    711
  - TPC and I/O Port Timing
    711
  - ITU Timing
    712
  - SCI Input/Output Timing
    713
  - DMAC Timing
    714
Appendix A Instruction Set

716
- Instruction List
  716
- Operation Code Map
  731
- Number of States Required for Execution
  734
Appendix B Internal I/O Register

743
- Addresses
  743
- Function
  751

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