Hitachi H8/3672F-ZTAT HD64F3672 Manuals

Manuals and User Guides for Hitachi H8/3672F-ZTAT HD64F3672. We have 1 Hitachi H8/3672F-ZTAT HD64F3672 manual available for free PDF download: Hardware Manual

Hitachi H8/3672F-ZTAT HD64F3672 Hardware Manual

Hitachi H8/3672F-ZTAT HD64F3672 Hardware Manual (305 pages)

Single-Chip Microcomputer

Brand: Hitachi | Category: Computer Hardware | Size: 1.17 MB

Table of Contents

Table of Contents
7
Section 1 Overview
25
Overview
25
Internal Block Diagram
26
Pin Arrangement
27
Pin Functions
29
Section 2 CPU

31
- Address Space and Memory Map
  32
- Register Configuration
  33
  - General Registers
    34
  - Program Counter (PC)
    35
  - Condition-Code Register (CCR)
    35
- Data Formats
  37
  - General Register Data Formats
    37
  - Memory Data Formats
    39
- Instruction Set
  40
- Addressing Modes and Effective Address Calculation
  51
  - Addressing Modes
    51
  - Effective Address Calculation
    53
- Basic Bus Cycle
  56
  - Access to On-Chip Memory (RAM, ROM)
    56
  - On-Chip Peripheral Modules
    57
- CPU States
  58
- Usage Notes
  59
Section 3 Exception Handling

65
- Exception Sources and Vector Address
  65
- Register Descriptions
  67
- Reset
  72
- Interrupt Exception Handling
  72
  - External Interrupts
    72
  - Internal Interrupts
    73
  - Interrupt Handling Sequence
    73
  - Interrupt Response Time
    75
- Usage Notes
  77
Section 4 Address Break

79
- Register Descriptions
  79
- Operation
  82
Section 5 Clock Pulse Generators

85
- System Clock Generator
  85
- Prescalers
  87
- Usage Notes
  87
  - Note on Oscillators
    87
  - Notes on Board Design
    88
Section 6 Power-Down Modes

89
- Register Descriptions
  89
- Mode Transitions and States of the LSI
  93
  - Sleep Mode
    95
  - Standby Mode
    95
  - Subsleep Mode
    95
- Operating Frequency in the Active Mode
  96
- Direct Transition
  96
- Module Standby Function
  96
Section 7 ROM

97
- Block Configuration
  97
- Register Descriptions
  98
- On-Board Programming Modes
  101
  - Boot Mode
    102
  - Programming/Erasing in User Program Mode
    104
- Flash Memory Programming/Erasing
  105
- Program/Erase Protection
  110
  - Hardware Protection
    110
  - Software Protection
    110
  - Error Protection
    110
Section 8 RAM

111
Section 9 I/O Ports

113
- Port 1
  113
  - Port Mode Register 1(PMR1)
    114
  - Port Control Register 1(PCR1)
    115
  - Port Data Register 1(PDR1)
    115
  - Port Pull-Up Control Register 1(PUCR1)
    116
  - Pin Functions
    116
- Port 2
  118
  - Port Control Register 2(PCR2)
    118
  - Port Data Register 2(PDR2)
    119
  - Pin Functions
    119
- Port 5
  120
  - Port Mode Register 5(PMR5)
    121
  - Port Control Register 5(PCR5)
    122
  - Port Data Register 5(PDR5)
    122
  - Port Pull-Up Control Register 5(PUCR5)
    123
  - Pin Functions
    123
- Port 7
  125
  - Port Control Register 7(PCR7)
    126
  - Port Data Register 7(PDR7)
    126
  - Pin Functions
    127
- Port 8
  128
  - Port Control Register 8(PCR8)
    128
  - Port Data Register 8(PDR8)
    129
  - Pin Functions
    129
- Port B
  131
  - Port Data Register B(PDRB)
    132
Section 10 Timer V

133
- Features
  133
- Input/Output Pins
  134
- Register Descriptions
  135
- Operation
  139
  - Timer V Operation
    139
- Timer V Application Examples
  143
  - Pulse Output with Arbitrary Duty Cycle
    143
  - Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input
    144
- Usage Notes
  145
Section 11 Timer W

147
- Features
  147
- Input/Output Pins
  149
- Register Descriptions
  150
  - Timer Mode Register W(TMRW)
    150
  - Timer Control Register W(TCRW)
    152
  - Timer Interrupt Enable Register W(TIERW)
    153
  - Timer Status Register W(TSRW)
    153
  - Timer I/O Control Register 0(TIOR0)
    155
  - Timer I/O Control Register 1(TIOR1)
    156
  - Timer Counter (TCNT)
    157
  - General Registers a to D (GRA to GRD)
    157
- Operation
  158
  - Normal Operation
    158
  - PWM Operation
    162
- Operation Timing
  166
  - TCNT Count Timing
    166
  - Output Compare Timing
    166
  - Input Capture Timing
    167
  - Timing of Counter Clearing by Compare Match
    168
  - Buffer Operation Timing
    168
  - Timing of IMFA to IMFD Flag Setting at Compare Match
    169
  - Timing of IMFA to IMFD Setting at Input Capture
    170
- Usage Notes
  171
Section 12 Watchdog Timer

173
- Features
  173
- Register Descriptions
  173
  - Timer Control/Status Register WD(TCSRWD)
    174
  - Timer Counter WD(TCWD)
    175
  - Timer Mode Register WD(TMWD)
    175
- Operation
  176
Section 13 Serial Communication Interface3 (SCI3)

177
- Features
  177
- Input/Output Pins
  179
- Register Descriptions
  179
  - Receive Shift Register (RSR)
    180
  - Receive Data Register (RDR)
    180
  - Transmit Shift Register (TSR)
    180
  - Transmit Data Register (TDR)
    180
  - Serial Mode Register (SMR)
    181
  - Serial Control Register 3 (SCR3)
    182
  - Serial Status Register (SSR)
    184
  - Bit Rate Register (BRR)
    186
- Operation in Asynchronous Mode
  191
  - Clock
    192
  - SCI3 Initialization
    193
  - Data Transmission
    194
  - Serial Data Reception
    196
- Operation in Clocked Synchronous Mode
  200
  - Clock
    200
  - SCI3 Initialization
    200
  - Serial Data Transmission
    201
  - Serial Data Reception (Clocked Synchronous Mode)
    203
  - Simultaneous Serial Data Transmission and Reception
    205
- Multiprocessor Communication Function
  207
  - Multiprocessor Serial Data Transmission
    209
  - Multiprocessor Serial Data Reception
    210
- Interrupts
  214
- Usage Notes
  215
Section 14 A/D Converter

217
- Features
  217
- Input/Output Pins
  219
- Register Description
  220
- Operation
  223
  - Single Mode
    223
  - Scan Mode
    223
  - Input Sampling and A/D Conversion Time
    224
  - External Trigger Input Timing
    225
- A/D Conversion Precision Definitions
  226
- Usage Notes
  227
  - Permissible Signal Source Impedance
    227
  - Influences on Absolute Precision
    227
Section 15 Power Supply Circuit

229
- When Using the Internal Power Supply Step-Down Circuit
  229
- When Not Using the Internal Power Supply Step-Down Circuit
  230
Section 16 Electrical Characteristics

231
- Absolute Maximum Ratings
  231
- Electrical Characteristics
  231
  - Power Supply Voltage and Operating Ranges
    231
  - DC Characteristics
    233
  - AC Characteristics
    238
  - A/D Converter Characteristics
    241
  - Watchdog Timer
    242
  - Flash Memory Characteristics (Preliminary)
    243
- Operation Timing
  245
- Output Load Circuit
  247
Appendix A Instruction Set

249
- Instruction List
  249
  - Data Transfer Instructions
    251
  - Arithmetic Instructions
    253
  - Bit Manipulation Instructions
    258
- Operation Code Map
  264
- Number of Execution States
  267
- Combinations of Instructions and Addressing Modes
  274
Appendix B Internal I/O Registers

275
- Register Addresses
  275
- Register Bits
  278
- B.2 Register Bits
  278
- Registers States in each Operating Mode
  281
Appendix C I/O Port Block Diagrams

284
- I/O Port Block
  284
- Port States in each Operating State
  299
Appendix D Product Code Lineup

300
Appendix E Package Dimensions

301

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