Hitachi HD64F2628 Manuals

Manuals and User Guides for Hitachi HD64F2628. We have 1 Hitachi HD64F2628 manual available for free PDF download: Hardware Manual

Hitachi HD64F2628 Hardware Manual (605 pages)

H8S/2628 Series 16-bit Single-Chip Microcomputer

Brand: Hitachi | Category: Computer Hardware | Size: 2.96 MB

General Precautions on Handling of Product
5
Preface
7
Table of Contents
9
Electrical Characteristics
29
Section 1 Overview

37
- Overview
  37
- Internal Block Diagram
  38
  - Figure 1.1 Internal Block Diagram
    38
  - Section 5 Interrupt Controller
    38
- Pin Arrangement
  39
- Figure 1.2 Pin Arrangement
  39
- Pin Functions
  40
Section 2 CPU

45
Section 3 MCU Operating Modes

83
- Operating Mode Selection
  83
- Register Descriptions
  83
- Pin Functions in each Operating Mode
  86
- Address Map
  87
- Figure 3.1 Address Map
  87
Section 4 Exception Handling

89
Section 5 Interrupt Controller

99
Section 6 PC Break Controller (PBC)

121
Section 7 Bus Controller

129
- Basic Timing
  129
- Bus Arbitration
  131
Section 8 Data Transfer Controller (DTC)

133
- Features
  133
- Figure 8.1 Block Diagram of DTC
  134
- Register Descriptions
  135
  - DTC Mode Register a (MRA)
    136
  - DTC Mode Register B (MRB)
    137
  - DTC Source Address Register (SAR)
    137
  - DTC Destination Address Register (DAR)
    137
  - DTC Transfer Count Register a (CRA)
    137
  - DTC Transfer Count Register B (CRB)
    138
  - DTC Enable Registers (DTCER)
    138
  - DTC Vector Register (DTVECR)
    139
- Activation Sources
  139
- Location of Register Information and DTC Vector Table
  140
- Figure 8.2 Block Diagram of DTC Activation Source Control
  140
- Figure 8.3 Location of DTC Register Information in Address Space
  141
- Table 8.1 Interrupt Sources, DTC Vector Addresses, and Corresponding Dtces
  142
- Operation
  143
- Procedures for Using DTC
  152
  - Activation by Interrupt
    152
  - Activation by Software
    152
- Examples of Use of the DTC
  152
  - Normal Mode
    152
  - Chain Transfer
    153
  - Software Activation
    154
- Usage Notes
  154
  - Module Stop Mode Setting
    154
  - On-Chip RAM
    155
  - DTCE Bit Setting
    155
Section 9 I/O Ports

157
- Table 9.1 Port Functions
  158
- Port 1
  161
  - Port 1 Data Direction Register (P1DDR)
    161
  - Port 1 Data Register (P1DR)
    162
  - Port 1 Register (PORT1)
    162
  - Pin Functions
    163
  - Table 9.2 P17 Pin Function
    163
  - Table 9.3 P16 Pin Function
    163
  - Table 9.4 P15 Pin Function
    163
  - Table 9.5 P14 Pin Function
    164
  - Table 9.6 P13 Pin Function
    164
  - Table 9.7 P12 Pin Function
    164
- Port 3
  165
  - Port 3 Data Direction Register (P3DDR)
    165
  - Table 9.8 P11 Pin Function
    165
  - Table 9.9 P10 Pin Function
    165
  - Port 3 Data Register (P3DR)
    166
  - Port 3 Register (PORT3)
    166
  - Port 3 Open-Drain Control Register (P3ODR)
    167
  - Pin Functions
    167
  - Table 9.10 P37 Pin Function
    167
  - Table 9.11 P36 Pin Function
    168
  - Table 9.12 P35 Pin Function
    168
  - Table 9.13 P34 Pin Function
    168
  - Table 9.14 P33 Pin Function
    168
  - Table 9.15 P32 Pin Function
    168
  - Table 9.16 P31 Pin Function
    168
- Port 4
  169
  - Port 4 Register (PORT4)
    169
- Port 7
  169
  - Table 9.17 P30 Pin Function
    169
  - Port 7 Data Direction Register (P7DDR)
    170
  - Port 7 Data Register (P7DR)
    170
  - Port 7 Register (PORT7)
    170
  - Pin Functions
    171
  - Table 9.18 P77 Pin Function
    171
  - Table 9.19 P76 Pin Function
    171
  - Table 9.20 P75 Pin Function
    171
  - Table 9.21 P74 Pin Function
    171
- Port 9
  172
  - Port 9 Register (PORT9)
    172
  - Table 9.22 P73 Pin Function
    172
  - Table 9.23 P72 Pin Function
    172
  - Table 9.24 P71 Pin Function
    172
  - Table 9.25 P70 Pin Function
    172
- Port a
  174
  - Port a Data Direction Register (PADDR)
    174
  - Port a Data Register (PADR)
    175
  - Port a Register (PORTA)
    175
  - Port a Pull-Up MOS Control Register (PAPCR)
    176
  - Port a Open-Drain Control Register (PAODR)
    176
  - Pin Functions
    177
  - Table 9.26 PA3 Pin Function
    177
  - Table 9.27 PA2 Pin Function
    177
  - Table 9.28 PA1 Pin Function
    177
  - Table 9.29 PA0 Pin Function
    177
- Port B
  178
  - Port B Data Direction Register (PBDDR)
    178
  - Port B Data Register (PBDR)
    179
  - Port B Register (PORTB)
    179
  - Port B Pull-Up MOS Control Register (PBPCR)
    180
  - Port B Open-Drain Control Register (PBODR)
    180
  - Pin Functions
    181
  - Table 9.30 PB7 Pin Function
    181
  - Table 9.31 PB6 Pin Function
    181
  - Table 9.32 PB5 Pin Function
    181
  - Table 9.33 PB4 Pin Function
    181
- Port C
  182
  - Table 9.34 PB3 Pin Function
    182
  - Table 9.35 PB2 Pin Function
    182
  - Table 9.36 PB1 Pin Function
    182
  - Table 9.37 PB0 Pin Function
    182
  - Port C Data Direction Register (PCDDR)
    183
  - Port C Data Register (PCDR)
    183
  - Port C Open-Drain Control Register (PCODR)
    184
  - Port C Pull-Up MOS Control Register (PCPCR)
    184
  - Port C Register (PORTC)
    184
  - Pin Functions
    185
  - Table 9.38 PC7 Pin Function
    185
  - Table 9.39 PC6 Pin Function
    185
  - Table 9.40 PC5 Pin Function
    186
  - Table 9.41 PC4 Pin Function
    186
  - Table 9.42 PC3 Pin Function
    186
  - Table 9.43 PC2 Pin Function
    186
  - Table 9.44 PC1 Pin Function
    187
  - Table 9.45 PC 0Pin Function
    187
- Port D
  188
- Port F
  190
  - Port F Data Direction Register (PFDDR)
    191
  - Port F Data Register (PFDR)
    192
  - Port F Register (PORTF)
    192
  - Pin Functions
    193
  - Table 9.46 PF7 Pin Function
    193
  - Table 9.47 PF6 Pin Function
    193
  - Table 9.48 PF5 Pin Function
    193
  - Table 9.49 PF4 Pin Function
    193
  - Table 9.50 PF3 Pin Function
    193
  - Table 9.51 PF2 Pin Function
    193
  - Table 9.52 PF1 Pin Function
    194
  - Table 9.53 PF0 Pin Function
    194
Section 10 16-Bit Timer Pulse Unit (TPU)

195
Section 11 8-Bit Timers

277
Section 12 Programmable Pulse Generator (PPG)

299
Section 13 Watchdog Timer

319
- Features
  319
- Figure 13.1 Block Diagram of WDT
  319
- Register Descriptions
  320
- Operation
  323
- Interrupts
  324
- Usage Notes
  324
Section 14 Serial Communication Interface (SCI)

327
Section 15 Hitachi Controller Area Network (HCAN)

391
- Features
  391
- Figure 15.1 HCAN Block Diagram
  392
- Input/Output Pins
  393
- Register Descriptions
  393
  - Table 15.1 HCAN Pins
    393
  - Master Control Register (MCR)
    394
  - General Status Register (GSR)
    395
  - Bit Configuration Register (BCR)
    397
  - Mailbox Configuration Register (MBCR)
    399
  - Transmit Wait Register (TXPR)
    400
  - Transmit Wait Cancel Register (TXCR)
    401
  - Transmit Acknowledge Register (TXACK)
    402
  - Abort Acknowledge Register (ABACK)
    403
  - Receive Complete Register (RXPR)
    404
  - Remote Request Register (RFPR)
    405
  - Interrupt Register (IRR)
    406
  - Mailbox Interrupt Mask Register (MBIMR)
    410
  - Interrupt Mask Register (IMR)
    411
  - Receive Error Counter (REC)
    412
  - Transmit Error Counter (TEC)
    412
  - Unread Message Status Register (UMSR)
    413
  - Local Acceptance Filter Masks (LAFML, LAFMH)
    414
  - Figure 15.2 Message Control Register Configuration
    416
  - Figure 15.3 Standard Format
    416
  - Figure 15.4 Extended Format
    416
  - Message Control (MC0 to MC15)
    416
  - Figure 15.5 Message Data Configuration
    418
  - HCAN Monitor Register (HCANMON)
    418
  - Message Data (MD0 to MD15)
    418
- Operation
  420
- Interrupt Sources
  436
- Table 15.4 HCAN Interrupt Sources
  436
- DTC Interface
  437
- Figure 15.15 DTC Transfer Flowchart
  437
- CAN Bus Interface
  438
- Usage Notes
  438
  - Module Stop Mode Setting
    438
  - Reset
    438
  - Figure 15.16 High-Speed Interface Using PCA82C250
    438
  - HCAN Sleep Mode
    439
  - Interrupts
    439
  - Error Counters
    439
  - Register Access
    439
  - HCAN Medium-Speed Mode
    439
  - Register Hold in Standby Modes
    439
  - Use on Bit Manipulation Instructions
    439
  - 15.8.10 HCAN TXCR Operation
    440
Section 16 Synchronous Serial Communication Unit (SSU)

441
Section 17 A/D Converter

463
- Features
  463
- Figure 17.1 Block Diagram of A/D Converter
  464
- Input/Output Pins
  465
- Table 17.1 Pin Configuration
  465
- Register Description
  466
- Operation
  470
  - Single Mode
    470
  - Scan Mode
    470
  - Input Sampling and A/D Conversion Time
    471
  - Figure 17.2 A/D Conversion Timing
    471
  - Table 17.3 A/D Conversion Time (Single Mode)
    472
  - Table 17.4 A/D Conversion Time (Scan Mode)
    472
  - External Trigger Input Timing
    473
- Interrupt Source
  473
- Figure 17.3 External Trigger Input Timing
  473
- Table 17.5 A/D Converter Interrupt Source
  473
- A/D Conversion Accuracy Definitions
  474
- Figure 17.4 A/D Conversion Accuracy Definitions
  475
- Figure 17.5 A/D Conversion Accuracy Definitions
  475
- Usage Notes
  476
Section 18 RAM

479
Section 19 ROM

481
- Features
  481
- Mode Transitions
  482
- Figure 19.1 Block Diagram of Flash Memory
  482
- Figure 19.2 Flash Memory State Transitions
  483
- Table 19.1 Differences between Boot Mode and User Program Mode
  483
- Figure 19.3 Boot Mode
  484
- Figure 19.4 User Program Mode
  485
- Block Configuration
  486
- Figure 19.5 Flash Memory Block Configuration
  486
- Input/Output Pins
  487
- Register Descriptions
  487
- On-Board Programming Modes
  491
- Flash Memory Emulation in RAM
  495
- Figure 19.7 Flowchart for Flash Memory Emulation in RAM
  495
- Figure 19.8 Example of RAM Overlap Operation
  496
- Flash Memory Programming/Erasing
  497
- Program/Erase Protection
  501
  - Hardware Protection
    501
  - Software Protection
    501
  - Error Protection
    501
- Programmer Mode
  502
- Power-Down States for Flash Memory
  502
- Table 19.6 Flash Memory Operating States
  502
Section 20 Clock Pulse Generator

503
Section 21 Power-Down Modes

513
Section 22 List of Registers

529
- Register Addresses (Address Order)
  530
- Register Bits
  546
- Register States in each Operating Mode
  564
Section 23 Electrical Characteristics

581
Appendix

599
- I/O Port States in each Pin State
  599
- Product Code Lineup
  600
- Package Dimensions
  600
- Figure C.1 FP-100M Package Dimensions
  600

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Hitachi HD64F2628 Manuals

Hitachi HD64F2628 Hardware Manual (605 pages)

Table of Contents

Section 1 Overview

Section 2 CPU

Section 3 MCU Operating Modes

Section 4 Exception Handling

Section 5 Interrupt Controller

Section 6 PC Break Controller (PBC)

Section 7 Bus Controller

Section 8 Data Transfer Controller (DTC)

Section 9 I/O Ports

Section 10 16-Bit Timer Pulse Unit (TPU)

Section 11 8-Bit Timers

Section 12 Programmable Pulse Generator (PPG)

Section 13 Watchdog Timer

Section 14 Serial Communication Interface (SCI)

Section 15 Hitachi Controller Area Network (HCAN)

Section 16 Synchronous Serial Communication Unit (SSU)

Section 17 A/D Converter

Section 18 RAM

Section 19 ROM

Section 20 Clock Pulse Generator

Section 21 Power-Down Modes

Section 22 List of Registers

Section 23 Electrical Characteristics

Appendix

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