Motorola PowerPC MPC750 Manuals

Manuals and User Guides for Motorola PowerPC MPC750. We have 2 Motorola PowerPC MPC750 manuals available for free PDF download: User Manual, Errata

Motorola PowerPC MPC750 User Manual

Motorola PowerPC MPC750 User Manual (468 pages)

RISC

Brand: Motorola | Category: Computer Hardware | Size: 33.89 MB

Table of Contents

Table of Contents
6
Audience
32
Organization
32
Suggested Reading
33
Conventions
36
Acronyms and Abbreviations
37
Terminology Conventions
40
Chapter 1

42
Overview

42
- MPC750 Microprocessor Overview
  42
- MPC750 Microprocessor Features
  45
- Overview of the MPC750 Microprocessor Features
  45
- Instruction Flow
  48
- Instruction Queue and Dispatch Unit
  49
- Branch Processing Unit (BPU)
  49
- Completion Unit
  50
- Independent Execution Units
  51
- Integer Units (Ius)
  51
- Floating-Point Unit (FPU)
  51
- Load/Store Unit (LSU)
  52
- System Register Unit (SRU)
  52
- Memory Management Units (Mmus)
  53
- On-Chip Instruction and Data Caches
  54
- L2 Cache Implementation (Not Supported in the MPC740)
  55
- System Interfacelbus Interface Unit (BIU)
  56
- Signals
  57
- Signal Configuration
  58
- Clocking
  60
- MPC750 Microprocessor: Implementation
  60
- Powerpc Registers and Programming Model
  62
- Instruction Set
  67
- Powerpc Instruction Set
  68
- MPC750 Microprocessor Instruction Set
  69
- On-Chip Cache Implementation
  70
- Powerpc Cache Model
  70
- Exception Model
  70
- Powerpc Exception Model
  70
- MPC7S0 Microprocessor Exception Implementation
  72
- Memory Management
  73
- Powerpc Memory Management Model
  74
- MPC7S0 Microprocessor Memory Management Implementation
  74
- Instruction Timing
  75
- Power Management
  77
- Thermal Management
  78
- Performance Monitor
  79
Chapter 2 MPC750 Processor Programming Model

80
Chapter 3

148
L 1 Instruction and Data Cache Operation

148
- Data Cache Organization
  150
- Instruction Cache Organization
  151
- Memory and Cache Coherency
  152
- Memory/Cache Access Attributes (WIMG Bits)
  153
- Mel Protocol
  154
- Mel Hardware Considerations
  156
- Coherency Precautions in Single Processor Systems
  157
- Coherency Precautions in Multiprocessor Systems
  157
- MPC750-Lnitiated Load/Store Operations
  157
- Performed Loads and Stores
  158
- Sequential Consistency of Memory Accesses
  158
- Atomic Memory References
  158
- Cache Control
  160
- Cache Control Parameters in HIDO
  160
- Data Cache Flash Invalidation
  160
- Data Cache Enabling/Disabling
  160
- Data Cache Locking
  161
- Instruction Cache Flash Invalidation
  161
- Instruction Cache Enabling/Disabling
  161
- Instruction Cache Locking
  162
- Cache Control Instructions
  162
- Data Cache Block Flush (Debt')
  164
- Instruction Cache Block Invalidate (Icbi)
  164
- Cache Operations
  165
- Cache Block Replacement/Castout Operations
  165
- Cache Flush Operations
  168
- Data Cache-Block-Fill Operations
  168
- Instruction Cache-Block-Fill Operations
  168
- Data Cache-Block-Push Operation
  169
- Enveloped High-Priority Cache-Block-Push Operation
  169
- Read Operations and the Mel Protocol
  170
- Bus Operations Caused by Cache Control Instructions
  171
- Snooping
  172
- Snoop Response to 60X Bus Transactions
  173
- Transfer Attributes
  175
- Bus Interface
  177
- Mel State Transactions
  179
Chapter 4 MPC750 Microprocessor Exceptions

183
- Exception Recognition and Priorities
  185
- Exception Processing
  188
- Enabling and Disabling Exceptions
  191
- Steps for Exception Processing
  191
- Setting MSR[RI]
  192
- Returning from an Exception Handler
  192
- Process Switching
  193
- Exception Definitions
  193
- System Reset Exception (Oxool00)
  194
- Machine Check Exception (Ox00200)
  195
- Machine Check Exception Enabled (MSR[ME] 1)
  197
- Checkstop State (MSR[ME] = 0)
  197
- Lsi Exception (Ox00400)
  198
- External Interrupt Exception (Ox00500)
  198
- Alignment Exception (Ox00600)
  199
- Program Exception (Ox00700)
  199
- Floating-Point Unavailable Exception (Ox00800)
  200
- Decrementer Exception (Ox00900)
  200
- System Call Exception (Oxoocoo)
  200
- Trace Exception (Oxoodoo)
  200
- Floating-Point Assist Exception (Oxooeoo)
  201
- Performance Monitor Interrupt (Oxoofoo)
  201
- Instruction Address Breakpoint Exception (Ox01300)
  202
- System Management Interrupt (Ox01400)
  203
- Thermal Management Interrupt Exception (Ox01700)
  205
Chapter 5

206
Memory Management

206
- MMU Overview
  207
- Memory Addressing
  209
- MMU Organization
  209
- Address Translation Mechanisms
  214
- Memory Protection Facilities
  216
- Page History Information
  217
- General Flow Ofmmu Address Translation
  217
- Real Addressing Mode and Block Address Translation Selection
  217
- Page Address Translation Selection
  219
- MMU Exceptions Summary
  221
- MMU Instructions and Register Summary
  223
- Real Addressing Mode
  225
- Block Address Translation
  226
- Memory Segment Model
  226
- Page History Recording
  226
- Referenced Bit
  227
- Changed Bit
  228
- Scenarios for Referenced and Changed Bit Recording
  228
- Page Memory Protection
  230
- TLB Description
  230
- TLB Organization
  230
- TLB Invalidation
  232
- Page Address Translation Summary
  233
- Page Table Search Operation
  235
- Page Table Updates
  239
- Segment Register Updates
  239
Chapter 6

240
Instruction Timing

240
- Terminology and Conventions
  240
- Instruction Timing Overview
  242
- Timing Considerations
  246
- General Instruction Flow
  247
- Instruction Fetch Timing
  250
- Cache Arbitration
  250
- Cache Hit
  250
- Cache Miss
  253
- L2 Cache Access Timing Considerations (MPC750 Only)
  254
- Instruction Dispatch and Completion Considerations
  255
- Rename Register Operation
  256
- Instruction Serialization
  256
- Execution Unit Timings
  257
- Branch Processing Unit Execution Timing
  257
- Branch Folding and Removal of Fall-Through Branch Instructions
  257
- Branch Instructions and Completion
  259
- Branch Prediction and Resolution
  260
- Static Branch Prediction
  261
- Predicted Branch Timing Examples
  261
- Integer Unit Execution Timing
  263
- Floating-Point Unit Execution Timing
  263
- Effect of Floating-Point Exceptions on Performance
  264
- Load/Store Unit Execution Timing
  264
- Effect of Operand Placement on Performance
  264
- Integer Store Gathering
  265
- System Register Unit Execution Timing
  266
- Memory Performance Considerations
  266
- Caching and Memory Coherency
  266
- Effect Oftlb Miss
  267
- Instruction Scheduling Guidelines
  268
- Branch, Dispatch, and Completion Unit Resource Requirements
  268
- Branch Resolution Resource Requirements
  269
- Dispatch Unit Resource Requirements
  269
- Completion Unit Resource Requirements
  269
- Instruction Latency Summary
  270
Chapter 7

278
Signal Descriptions

278
- Signal Configuration
  280
- Signal Descriptions
  281
- Address Bus Arbitration Signals
  281
- Bus Request (BR)-Output
  281
- Bus Grant (BG)-Input
  281
- Address Bus Busy (ABB)
  282
- Address Bus Busy (ABB)-Output
  282
- Address Bus Busy (ABB)-Input
  282
- Address Transfer Start Signals
  283
- Transfer Start (TS)
  283
- Transfer Start (TS)-Output
  283
- Transfer Start (TS)-Input
  283
- Address Transfer Signals
  283
- Address Bus (A[0-31])
  283
- Address Bus Parity (AP[0-3])
  284
- Address Transfer Attribute Signals
  285
- Transfer Type (TT[O-4])
  285
- Transfer Type (TT[O-4])-Output
  285
- Transfer Burst (TBST)
  289
- Transfer Burst (TBST)-Output
  289
- Transfer Burst (TBST)-Input
  289
- Cache Inhibit (CI)-Output
  289
- Write-Through (WT)-Output
  290
- Global (GBL)
  290
- Global (GBL)-Output
  290
- Global (GBL)-Input
  290
  - Address Acknowledge (AACK)-Input
    291
  - Address Retry (ARTRY)
    291
    
    Address Retry (ARTRY)-Output
    291
    
    Address Retry (ARTRY)-Input
    292
- Data Bus Arbitration Signals
  292
  - Data Bus Grant (DBG)-Input
    292
  - Data Bus Write Only (DBWO)-Input
    293
  - Data Bus Busy (DBB)
    293
    
    Data Bus Busy (DBB)-Output
    293
    
    Data Bus Busy (DBB)-Input
    293
- Data Transfer Signals
  294
  - Data Bus (DH[0-31], DL[0-31])
    295
  - Data Bus Disable (DBDIS)-Input
    296
- Data Transfer Termination Signals
  296
  - Transfer Acknowledge (TA)-Input
    296
  - Transfer Error Acknowledge (TEA)-Input
    297
- System Status Signals
  298
  - Interrupt (INT)-Input
    298
  - System Management Interrupt (SMI)-Input
    298
  - Machine Check Interrupt (MCP)-Input
    298
  - Reset Signals
    300
    
    Hard Reset (HRESET)-Input
    300
    
    Soft Reset (SRESET)-Input
    300
  - Processor Status Signals
    300
    
    Quiescent Request (QREQ)-Output
    301
    
    Quiescent Acknowledge (QACK)-Input
    301
    
    Reservation (RSRV)-Output
    301
    
    Time Base Enable (TBEN)-Input
    301
    
    TLBI Sync (TLBISYNC)-Input
    302
    
    L2 Cache Interface
    302
  - L2 Address (L2ADDR[16-0])-Output
    302
- L2 Chip Enable (L2CE)-Output
  303
- L2 Write Enable (L2WE)-Output
  304
- L2 Low-Power Mode Enable (L2ZZ)-Output
  305
- IEEE 1149.1A-1993 Interface Description
  305
- Clock Signals
  306
- System Clock (SYSCLK)-Input
  306
- Clock out (CLK_OUT)-Output
  306
- Power and Ground Signals
  307
Chapter 8

308
System Interface Operation

308
- MPC750 System Interface Overview
  308
- Operation of the L2 Cache
  311
- Operation of the System Interface
  311
- Direct-Store Accesses
  312
- Memory Access Protocol
  313
- Arbitration Signals
  315
- Address Pipelining and Split-Bus Transactions
  316
- Address Bus Tenure
  317
- Address Bus Arbitration
  317
- Address Transfer
  319
- Address Bus Parity
  320
- Address Transfer Attribute Signals
  320
- Transfer Type (TT[0-4]) Signals
  320
- Transfer Size (TSIZ[0-2]) Signals
  320
- Write-Through (WT) Signal
  321
- Cache Inhibit (CI) Signal
  321
- Alignment of External Control Instructions
  324
- Address Transfer Termination
  324
- Data Bus Tenure
  326
- Data Bus Arbitration
  326
- Using the DBB Signal
  327
- Data Bus Write Only
  328
- Data Transfer
  328
- Data Transfer Termination
  329
- Normal Single-Beat Termination
  329
- Data Transfer Termination Due to a Bus Error
  333
- Memory Coherency-Mel Protocol
  333
- Timing Examples
  335
- Optional Bus Configuration
  341
- No-DRTRY Mode
  341
- Interrupt, Checkstop, and Reset Signals
  342
- External Interrupts
  342
- Checkstops
  342
- Reset Inputs
  342
- System Quiesce Control Signals
  342
- Processor State Signals
  343
- TLBISYNC Input
  343
- IEEE 1149.1A-1993 Compliant Interface
  344
- JTAG/COP Interface
  344
- Using Data Bus Write Only
  344
Chapter 9

348
L2 Cache Interface Operation

348
- L2 Cache Interface Overview
  348
- L2 Cache Operation
  349
- L2 Cache Control Register (L2CR)
  351
- L2 Cache Initialization
  353
- L2 Cache Global Invalidation
  354
- L2 Cache Test Features and Methods
  354
- L2CR Support for L2 Cache Testing
  354
- L2 Cache Testing
  355
- L2 Clock Configuration
  356
- L2 Cache Sramtiming Examples
  356
- Flow-Through Burst SRAM
  356
- Pipelined Burst SRAM
  358
- Late-Write SRAM
  359
Chapter 10 Power and Thermal Management

362
- Dynamic Power Management
  362
- Programmable Power Modes
  362
- Power Management Modes
  363
- Full-Power Mode with DPM Disabled
  363
- Full-Power Mode with DPM Enabled
  363
- Doze Mode
  364
- Nap Mode
  364
- Sleep Mode
  365
- Power Management Software Considerations
  366
- Thermal Assist Unit
  367
- Thermal Assist Unit Overview
  367
- Thermal Assist Unit Operation
  369
- TAU Single Threshold Mode
  369
- TAU Dual-Threshold Mode
  370
- MPC750 Junction Temperature Determination
  371
- Power Saving Modes and TAU Operation
  371
- Instruction Cache Throttling
  371
Chapter 11

374
Performance Monitor

374
Performance Monitor Interrupt

375
Appendix A Powerpc Instruction Set Listings

386
Appendix B Instructions Not Implemented

434

Motorola PowerPC MPC750 Errata

Motorola PowerPC MPC750 Errata (4 pages)

RISC Microprocessor

Brand: Motorola | Category: Computer Hardware | Size: 0.09 MB

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