NEC V850E/CA1 ATOMIC Manuals

Manuals and User Guides for NEC V850E/CA1 ATOMIC. We have 1 NEC V850E/CA1 ATOMIC manual available for free PDF download: Preliminary User's Manual

NEC V850E/CA1 ATOMIC Preliminary User's Manual (601 pages)

32-/16-bit Single-Chip Microcontroller

Brand: NEC | Category: Microcontrollers | Size: 3.45 MB

Table of Contents
7
Chapter 1 Introduction

21
- General
  
  21
- Device Features
  
  22
- Application Fields
  
  23
- Ordering Information
  
  23
- Pin Configuration (Top View)
  
  24
  - Figure 1-1: Pin Configuration of the Μpd70(F)3123 Microcontroller
    24
- Configuration of Function Block
  
  26
Chapter 2 Pin Functions

29
Chapter 3 CPU Function

53
Chapter 4 Bus Control Function

119
- Features
  
  119
- Bus Control Pins
  
  119
- Memory Block Function
  
  120
  - Figure 4-1: Memory Block Function
    120
    
    Chip Select Control Function
    121
    
    Figure 4-2: Chip Area Select Control Registers 0, 1 (1/2)
    121
- Bus Cycle Type Control Function
  
  123
  - Bus Cycle Type Configuration
    123
- Bus Access
  
  124
  - Number of Access Clocks
    124
  - Bus Sizing Function
    124
  - Table 4-1: Number of Bus Access Clocks
    124
  - Endian Control Function
    125
  - Figure 4-3: Big Endian Addresses Within Word
    125
  - Figure 4-4: Little Endian Addresses Within Word
    125
  - Bus Width
    126
- Wait Function
  
  138
- Idle State Insertion Function
  
  141
- Bus Priority Order
  
  142
  - Table 4-2: Bus Priority Order
    142
- Boundary Operation Conditions
  
  143
  - Program Space
    143
  - Data Space
    143
Chapter 5 Memory Access Control Function

145
- SRAM, External ROM, External I/O Interface
  
  145
- Page ROM Controller (ROMC)
  
  153
  - Features
    153
  - Page ROM Connections
    154
  - Figure 5-3: Example of Page ROM Connections
    154
  - On-Page/Off
    155
  - Figure 5-4: On-Page/Off-Page Judgment During Page ROM Connection (1/2)
    155
  - Page ROM Configuration Register (PRC)
    157
  - Figure 5-5: Page ROM Configuration Register (PRC)
    157
  - Page ROM Access
    158
  - Figure 5-6: Page ROM Access Timing (1/4)
    158
Chapter 6 DMA Functions (DMA Controller)

163
Chapter 7 Interrupt/Exception Processing Function

183
Chapter 8 Clock Generator

225
- Features
  
  225
- Configuration
  
  225
  - Figure 8-1: Block Diagram of the Clock Generator
    225
- Main System Clock Oscillator
  
  226
  - Figure 8-2: Main System Clock Oscillator
    226
- Control Registers
  
  227
  - Clock Control Register (CKC)
    227
  - PLL Status Register (PSTAT)
    228
  - Clock Select Pin
    228
  - Table 8-1: PLL Mode / Direct Mode
    228
  - Table 8-2: Relation System Clock to Resonator Frequency
    229
  - Table 8-3: CESEL Setting
    229
- Power Saving Functions
  
  230
- Register Description
  
  240
  - Power Save Control Register (PSC)
    240
  - Power Save Mode Register (PSM)
    242
- Securing Oscillation Stabilization Time
  
  243
Chapter 9 Timer / Counter (Real Time Pulse Unit)

247
- Timer D
  
  247
  - Features (Timer D)
    247
  - Function Overview (Timer D)
    247
  - Basic Configuration
    248
  - Figure 9-1: Block Diagram of Timer D
    248
  - Table 9-1: Timer D Configuration List
    248
  - Figure 9-2: Timer D Registers 0, 1 (TMD0, TMD1)
    249
  - Figure 9-3: Timer D Compare Registers 0, 1 (CMD0 to CMD1)
    250
  - Figure 9-4: Example of Timing During TMD Operation
    251
  - Control Register
    252
  - Figure 9-5: Timer D Control Register 0, 1 (TMCD0 to TMCD1)
    252
  - Operation
    253
  - Figure 9-6: TMD Compare Operation Example
    254
  - Application Example
    255
  - Precautions
    255
- Timer E
  
  256
Chapter 10 Watch Timer

299
- Function
  
  299
  - Figure 10-1: Block Diagram of Watch Timer
    299
- Configuration
  
  300
  - Table 10-1: Interval Time of Interval Timer (F SUB = 4 Mhz)
    300
  - Table 10-2: Configuration of Watch Timer
    300
- Watch Timer Control Register
  
  301
  - Figure 10-2: Watch Timer Mode Control Register (WTM)
    301
- Operations
  
  303
Chapter 11 Watchdog Timer

305
- Watchdog Timer Mode
  
  305
  - Figure 11-1: Block Diagram of Watchdog Timer Unit
    305
  - Table 11-1: Runaway Detection Time by Watchdog Timer
    305
- Control Register
  
  306
  - Watchdog Timer Mode Register (WDTM)
    306
- Operation
  
  307
  - Operating as Watchdog Timer
    307
  - Table 11-2: Runaway Detection Time by Watchdog Timer
    307
Chapter 12 Serial Interface Function

309
Chapter 13 FCAN Interface Function

369
Chapter 14 A/D Converter

487
Chapter 15 LCD Controller/Driver

513
Chapter 16 Port Functions

525
- Features
  
  525
- Port Configuration
  
  526
- Pin Functions of each Port
  
  538
  - Port 1
    538
  - Figure 16-9: Port 1 (P1)
    538
  - Figure 16-10: Port 1 Mode Register (PM1)
    538
  - Figure 16-11: Port 1 Mode Control Register (PMC1)
    539
  - Port 2
    540
  - Figure 16-12: Port 2 (P2)
    540
  - Figure 16-13: Port 2 Mode Register (PM2)
    540
  - Figure 16-14: Port 2 Mode Control Register (PMC2)
    541
  - Port 3
    542
  - Figure 16-15: Port 3 (P3)
    542
  - Figure 16-16: Port 3 Mode Register (PM3)
    542
  - Figure 16-17: Port 3 Mode Control Register (PMC3)
    543
  - Port 4
    544
  - Figure 16-18: Port 4 (P4)
    544
  - Figure 16-19: Port 4 Mode Register (PM4)
    544
  - Figure 16-20: Port 4 Mode Control Register (PMC4)
    545
  - Port 5
    546
  - Figure 16-21: Port 5 (P5)
    546
  - Figure 16-22: Port 5 Mode Register (PM5)
    546
  - Figure 16-23: Port 5 Mode Control Register (PMC5)
    547
  - Port 6
    548
  - Figure 16-24: Port 6 (P6)
    548
  - Figure 16-25: Port 6 Mode Register (PM6)
    548
  - Figure 16-26: Port 6 Mode Control Register (PMC6)
    549
- Port al
  
  550
- Port AH
  
  551
- Port DL
  
  553
- Port CS
  
  555
- Port CT
  
  557
- Port CM
  
  559
Chapter 17 RESET Function

561
- Features
  
  561
- Pin Functions
  
  561
- Initialization
  
  563
  - Table 17-2: Initial Values of CPU and Internal RAM after Reset
    563
Chapter 18 Voltage Regulator

565
- Outline
  
  565
- Operation
  
  565
  - Figure 18-1: Regulator
    565
Chapter 19 Internal Voltage Comparator

567
- Features
  
  567
  - Figure 19-1: Block Diagram of Voltage Comparator
    567
- Voltage Comparator Functions
  
  568
  - Table 19-1: Power Supply Voltage Operating Modes
    568
    
    Figure 19-2: Internal Voltage Comparator
    569
    
    Internal Voltage Comparator Control Register (VCMPM)
    570
Chapter 20 Flash Memory (Μpd70F3123)

571
- Features
  
  571
- Writing by Flash Writer
  
  572
- Programming Environment
  
  572
  - Figure 20-1: Programming Environment in Conjunction with External Flash Writer
    572
- Communication System
  
  573
  - Figure 20-2: Flash Writer Communication Via CSI0
    573
- Flash Programming Circuitry
  
  574
  - Figure 20-3: Application Example for Flash Selfprogramming
    574
- Pin Handling
  
  575
  - Vpp0 /V
    575
  - Pp0 Pp1
    575
  - PP1 Pins
    575
  - Figure 20-4: Pin Handling of V
    575
  - Pins
    575
    
    Serial Interface Pins
    576
    
    Figure 20-5: Conflict between Flash Writer and Other Output Pin
    576
    
    Figure 20-6: Malfunction of Other Input Pins
    577
    
    RESET Pin
    578
    
    NMI Pin
    578
    
    MODE Pin
    578
    
    Port Pins
    578
    
    Other Signal Pins
    578
    
    Power Supply
    578
    
    Figure 20-7: Conflict between Flash Writer Reset Line and Reset Signal Generation Circuit
    578
- Programming Method
  
  579
- Selfprogramming Mode
  
  580
  - Figure 20-9: Configuration in Selfprogramming Mode
    580
- Secure Selfprogramming
  
  581
  - General Description
    581
  - Signature Structure
    581
  - Secure Selfprogramming Flow
    581
  - Figure 20-10: Secure Selfprogramming Flow (1/2)
    582
  - Advantages of Secure Selfprogramming
    583
Appendix A Instruction Set List

585
Appendix B Index

593

NEC Categories

NEC V850E/CA1 ATOMIC Manuals

NEC V850E/CA1 ATOMIC Preliminary User's Manual (601 pages)

Table of Contents

Chapter 1 Introduction

General

Device Features

Application Fields

Ordering Information

Pin Configuration (Top View)

Configuration of Function Block

Chapter 2 Pin Functions

List of Pin Functions

Description of Pin Functions

Types of Pin I/O Circuit and Connection of Unused Pin

Chapter 3 CPU Function

Features

CPU Register Set

Operation Modes

Address Space

Specific Registers

Chapter 4 Bus Control Function

Features

Bus Control Pins

Memory Block Function

Bus Cycle Type Control Function

Bus Access

Wait Function

Idle State Insertion Function

Bus Priority Order

Boundary Operation Conditions

Chapter 5 Memory Access Control Function

SRAM, External ROM, External I/O Interface

Page ROM Controller (ROMC)

Chapter 6 DMA Functions (DMA Controller)

Features

Configuration

Control Registers

DMA Bus States

Transfer Mode

Transfer Types

Transfer Object

DMA Channel Priorities

Next Address Setting Function

DMA Transfer Start Factors

Forcible Interruption

DMA Transfer End

Forcible Termination

Precautions

Chapter 7 Interrupt/Exception Processing Function

Features

Non-Maskable Interrupts

Maskable Interrupts

Noise Elimination Circuit

Software Exception

Exception Trap

Multiple Interrupt Processing Control

Interrupt Response Time

Periods in Which Interrupts Are Not Acknowledged

Chapter 8 Clock Generator

Features

Configuration

Main System Clock Oscillator

Control Registers

Power Saving Functions

Register Description

Securing Oscillation Stabilization Time

Chapter 9 Timer / Counter (Real Time Pulse Unit)

Timer D

Timer E

Chapter 10 Watch Timer

Function

Configuration

Watch Timer Control Register

Operations

Chapter 11 Watchdog Timer

Watchdog Timer Mode

Control Register

Operation

Chapter 12 Serial Interface Function

Features