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1
Silicon Laboratories C8051T321 manual available for free PDF download: Manual
Silicon Laboratories C8051T321 Manual (299 pages)
Full Speed USB EPROM MCU Family
Brand:
Silicon Laboratories
| Category:
Microcontrollers
| Size: 1.69 MB
Table of Contents
Table of Contents
3
1 System Overview
15
Figure 1.1. C8051T620/1 Block Diagram
16
Figure 1.2. C8051T626/7 Block Diagram
17
Figure 1.3. C8051T320/2 Block Diagram
18
Figure 1.4. C8051T321/3 Block Diagram
19
Figure 1.5. Typical Bus-Powered Connections
20
2 Ordering Information
21
Table 2.1. Product Selection Guide
21
3 Pin Definitions
22
Table 3.1. Pin Definitions for the C8051T620/1/6/7 & C8051T320/1/2/3
22
Figure 3.1. QFN-32 Pinout Diagram (Top View)
25
Figure 3.2. LQFP-32 Pinout Diagram (Top View)
26
Figure 3.3. QFN-28 Pinout Diagram (Top View)
27
4 LQFP-32 Package Specifications
28
Figure 4.1. LQFP-32 Package Drawing
28
Figure 4.2. LQFP-32 Recommended PCB Land Pattern
29
5 Package Specifications
30
Figure 5.1. QFN-32 Package Drawing
30
Figure 5.2. QFN-32 Recommended PCB Land Pattern
31
6 Package Specifications
32
Figure 6.1. QFN-28 Package Drawing
32
Figure 6.2. QFN-28 Recommended PCB Land Pattern
33
7 Electrical Characteristics
34
Absolute Maximum Specifications
34
Table 7.1. Absolute Maximum Ratings
34
Electrical Characteristics
35
Table 7.2. Global Electrical Characteristics
35
Table 7.3. Port I/O DC Electrical Characteristics
36
Table 7.4. Reset Electrical Characteristics
36
Table 7.5. Internal Voltage Regulator Electrical Characteristics
37
Table 7.6. EPROM Electrical Characteristics
38
Table 7.7. Internal High-Frequency Oscillator Electrical Characteristics
38
Table 7.8. Internal Low-Frequency Oscillator Electrical Characteristics
39
Table 7.9. External Oscillator Electrical Characteristics
39
Table 7.10. ADC0 Electrical Characteristics
40
Table 7.11. Temperature Sensor Electrical Characteristics
41
Table 7.12. Voltage Reference Electrical Characteristics
41
Table 7.13. Comparator Electrical Characteristics
42
Table 7.14. USB Transceiver Electrical Characteristics
43
Typical Performance Curves
44
Figure 7.1. Normal Mode Digital Supply Current Vs. Frequency (MPCE = 1)
44
Figure 7.2. Idle Mode Digital Supply Current Vs. Frequency (MPCE = 1)
44
8 Bit ADC (ADC0, C8051T620/6/7 and C8051T320/1 Only)
45
Figure 8.1. ADC0 Functional Block Diagram
45
Output Code Formatting
46
8-Bit Mode
46
Modes of Operation
46
Starting a Conversion
46
Figure 8.2. 10-Bit ADC Track and Conversion Example Timing
47
Tracking Modes
47
Figure 8.3. ADC0 Equivalent Input Circuits
48
Settling Time Requirements
48
SFR Definition 8.1. ADC0CF: ADC0 Configuration
49
SFR Definition 8.2. ADC0H: ADC0 Data Word MSB
50
SFR Definition 8.3. ADC0L: ADC0 Data Word LSB
50
SFR Definition 8.4. ADC0CN: ADC0 Control
51
Programmable Window Detector
52
SFR Definition 8.5. ADC0GTH: ADC0 Greater-Than Data High Byte
52
SFR Definition 8.6. ADC0GTL: ADC0 Greater-Than Data Low Byte
52
SFR Definition 8.7. ADC0LTH: ADC0 Less-Than Data High Byte
53
SFR Definition 8.8. ADC0LTL: ADC0 Less-Than Data Low Byte
53
Window Detector Example
54
Figure 8.4. ADC Window Compare Example: Right-Justified Data
54
Figure 8.5. ADC Window Compare Example: Left-Justified Data
54
ADC0 Analog Multiplexer (C8051T620/6/7 and C8051T320/1 Only)
55
Figure 8.6. ADC0 Multiplexer Block Diagram
55
SFR Definition 8.9. AMX0P: AMUX0 Positive Channel Select
56
9 Temperature Sensor (C8051T620/6/7 and C8051T320/1 Only)
57
Figure 9.1. Temperature Sensor Transfer Function
57
Calibration
58
Figure 9.2. TOFFH and TOFFL Calibration Value Orientation
58
Figure 9.3. Temperature Sensor Error with 1-Point Calibration at 0 Celsius
58
10 Voltage Reference Options
59
Figure 10.1. Voltage Reference Functional Block Diagram
59
SFR Definition 10.1. REF0CN: Reference Control
60
11 Voltage Regulators (REG0 and REG1)
61
Voltage Regulator (REG0)
61
Regulator Mode Selection
61
VBUS Detection
61
Figure 11.1. REG0 Configuration: USB Bus-Powered
61
Figure 11.2. REG0 Configuration: USB Self-Powered
62
Figure 11.3. REG0 Configuration: USB Self-Powered, Regulator Disabled
62
Figure 11.4. REG0 Configuration: no USB Connection
63
Voltage Regulator (REG1)
64
SFR Definition 11.1. REG01CN: Voltage Regulator Control
65
12 Microcontroller
66
Figure 12.1. CIP-51 Block Diagram
66
Instruction Set
67
Instruction and CPU Timing
67
Table 12.1. CIP-51 Instruction Set Summary
68
Register Descriptions
73
SFR Definition 12.1. DPL: Data Pointer Low Byte
73
SFR Definition 12.2. DPH: Data Pointer High Byte
73
SFR Definition 12.3. SP: Stack Pointer
74
SFR Definition 12.4. ACC: Accumulator
74
SFR Definition 12.5. B: B Register
74
SFR Definition 12.6. PSW: Program Status Word
75
13 Prefetch Engine
76
SFR Definition 13.1. PFE0CN: Prefetch Engine Control
76
14 Comparator0 and Comparator1
77
Figure 14.1. Comparator0 Functional Block Diagram
77
Figure 14.2. Comparator1 Functional Block Diagram
78
Figure 14.3. Comparator Hysteresis Plot
79
SFR Definition 14.1. CPT0CN: Comparator0 Control
80
SFR Definition 14.2. CPT0MD: Comparator0 Mode Selection
81
SFR Definition 14.3. CPT1CN: Comparator1 Control
82
SFR Definition 14.4. CPT1MD: Comparator1 Mode Selection
83
Comparator Multiplexers
84
Figure 14.4. Comparator Input Multiplexer Block Diagram
84
SFR Definition 14.5. CPT0MX: Comparator0 MUX Selection
85
SFR Definition 14.6. CPT1MX: Comparator1 MUX Selection
86
15 Memory Organization
87
Figure 15.1. C8051T620/1 and C8051T320/1/2/3 Memory Map
87
Program Memory
88
Figure 15.2. C8051T626/7 Memory Map
88
Derivative ID
89
Figure 15.3. Program Memory Map
89
Serialization
89
Temperature Offset Calibration
89
Data Memory
90
Bit Addressable Locations
90
General Purpose Registers
90
Internal RAM
90
Stack
90
Accessing USB FIFO Space
91
External RAM
91
SFR Definition 15.1. EMI0CN: External Memory Interface Control
91
Figure 15.4. C8051T620/1 and C8051T320/1/2/3 USB FIFO Space and
92
XRAM Memory Map with USBFAE Set to 1
92
Figure 15.5. C8051T626/7 USB FIFO Space and XRAM Memory Map
93
With USBFAE Set to 1
93
SFR Definition 15.2. EMI0CF: External Memory Configuration
94
16 Special Function Registers
95
Table 16.1. Special Function Register (SFR) Memory Map
95
Table 16.2. Special Function Registers
96
17 Interrupts
101
MCU Interrupt Sources and Vectors
102
Interrupt Priorities
102
Interrupt Latency
102
Interrupt Register Descriptions
102
Table 17.1. Interrupt Summary
103
SFR Definition 17.1. IE: Interrupt Enable
104
SFR Definition 17.2. IP: Interrupt Priority
105
SFR Definition 17.3. EIE1: Extended Interrupt Enable 1
106
SFR Definition 17.4. EIP1: Extended Interrupt Priority 1
107
SFR Definition 17.5. EIE2: Extended Interrupt Enable 2
108
SFR Definition 17.6. EIP2: Extended Interrupt Priority 2
109
INT0 and INT1 External Interrupt Sources
110
SFR Definition 17.7. IT01CF: INT0/INT1 Configurationo
111
18 Program Memory (EPROM)
112
Programming the EPROM Memory
112
EPROM Programming over the C2 Interface
112
EPROM In-Application Programming
113
Security Options
114
EPROM Writing Guidelines
114
VDD Maintenance and the VDD Monitor
114
Table 18.1. Security Byte Decoding
114
PSWE Maintenance
115
System Clock
115
Program Memory CRC
115
Performing 32-Bit Crcs on Full EPROM Content
115
Performing 16-Bit Crcs on 256-Byte EPROM Blocks
115
SFR Definition 18.1. PSCTL: Program Store R/W Control
116
SFR Definition 18.2. MEMKEY: EPROM Memory Lock and Key
116
SFR Definition 18.3. IAPCN: In-Application Programming Control
117
19 Power Management Modes
118
Idle Mode
118
Stop Mode
119
Suspend Mode
119
SFR Definition 19.1. PCON: Power Control
120
20 Reset Sources
121
Figure 20.1. Reset Sources
121
Power-On Reset
122
Power-Fail Reset / VDD Monitor
122
Figure 20.2. Power-On and VDD Monitor Reset Timing
122
External Reset
124
Missing Clock Detector Reset
124
Comparator0 Reset
124
SFR Definition 20.1. VDM0CN: VDD Monitor Control
124
PCA Watchdog Timer Reset
125
EPROM Error Reset
125
Software Reset
125
USB Reset
125
SFR Definition 20.2. RSTSRC: Reset Source
126
21 Oscillators and Clock Selection
127
Figure 21.1. Oscillator Options
127
System Clock Selection
128
USB Clock Selection
128
SFR Definition 21.1. CLKSEL: Clock Select
129
Programmable Internal High-Frequency (H-F) Oscillator
130
Internal Oscillator Suspend Mode
130
SFR Definition 21.2. OSCICL: Internal H-F Oscillator Calibration
130
SFR Definition 21.3. OSCICN: Internal H-F Oscillator Control
131
Clock Multiplier
132
SFR Definition 21.4. CLKMUL: Clock Multiplier Control
132
Programmable Internal Low-Frequency (L-F) Oscillator
133
Calibrating the Internal L-F Oscillator
133
SFR Definition 21.5. OSCLCN: Internal L-F Oscillator Control
133
External Oscillator Drive Circuit
134
External Crystal Mode
134
Figure 21.2. External Crystal Example
135
External Capacitor Example
136
External RC Example
136
SFR Definition 21.6. OSCXCN: External Oscillator Control
137
22 Port Input/Output
138
Figure 22.1. Port I/O Functional Block Diagram
138
Port I/O Modes of Operation
139
Figure 22.2. Port I/O Cell Block Diagram
139
Port Pins Configured for Analog I/O
139
Port Pins Configured for Digital I/O
139
Interfacing Port I/O to 5 V Logic
140
Assigning Port I/O Pins to Analog and Digital Functions
140
Assigning Port I/O Pins to Analog Functions
140
Assigning Port I/O Pins to Digital Functions
140
Assigning Port I/O Pins to External Digital Event Capture Functions
141
Priority Crossbar Decoder
142
Figure 22.3. Priority Crossbar Decoder Potential Pin Assignments
143
Figure 22.4. Priority Crossbar Decoder Example 1-No Skipped Pins
144
Figure 22.5. Priority Crossbar Decoder Example 2-Skipping Pins
145
Port I/O Initialization
146
SFR Definition 22.1. XBR0: Port I/O Crossbar Register 0
147
SFR Definition 22.2. XBR1: Port I/O Crossbar Register 1
148
Port Match
149
SFR Definition 22.3. XBR2: Port I/O Crossbar Register 2
149
SFR Definition 22.4. P0MASK: Port 0 Mask Register
150
SFR Definition 22.5. P0MAT: Port 0 Match Register
150
SFR Definition 22.6. P1MASK: Port 1 Mask Register
151
SFR Definition 22.7. P1MAT: Port 1 Match Register
151
Special Function Registers for Accessing and Configuring Port I/O
152
SFR Definition 22.8. P0: Port 0
152
SFR Definition 22.9. P0MDIN: Port 0 Input Mode
153
SFR Definition 22.10. P0MDOUT: Port 0 Output Mode
153
SFR Definition 22.11. P0SKIP: Port 0 Skip
154
SFR Definition 22.12. P1: Port 1
154
SFR Definition 22.13. P1MDIN: Port 1 Input Mode
155
SFR Definition 22.14. P1MDOUT: Port 1 Output Mode
155
SFR Definition 22.15. P1SKIP: Port 1 Skip
156
SFR Definition 22.16. P2: Port 2
156
SFR Definition 22.17. P2MDIN: Port 2 Input Mode
157
SFR Definition 22.18. P2MDOUT: Port 2 Output Mode
157
SFR Definition 22.19. P2SKIP: Port 2 Skip
158
SFR Definition 22.20. P3: Port 3
158
SFR Definition 22.21. P3MDOUT: Port 3 Output Mode
159
23 Universal Serial Bus Controller (USB0)
160
Figure 23.1. USB0 Block Diagram
160
Endpoint Addressing
161
USB Transceiver
161
Table 23.1. Endpoint Addressing Scheme
161
SFR Definition 23.1. USB0XCN: USB0 Transceiver Control
162
USB Register Access
163
Figure 23.2. USB0 Register Access Scheme
163
SFR Definition 23.2. USB0ADR: USB0 Indirect Address
164
SFR Definition 23.3. USB0DAT: USB0 Data
165
Table 23.2. USB0 Controller Registers
166
USB Clock Configuration
168
FIFO Management
169
Figure 23.3. C8051T620/1 and C8051T320/1/2/3 USB FIFO Allocation
169
FIFO Double Buffering
170
FIFO Split Mode
170
Figure 23.4. C8051T626/7 USB FIFO Allocation
170
FIFO Access
171
Table 23.3. FIFO Configurations
171
Function Addressing
172
Function Configuration and Control
173
Interrupts
176
Endpoint0
181
Endpoint0 in Transactions
182
Endpoint0 SETUP Transactions
182
Endpoint0 out Transactions
183
The Serial Interface Engine
181
Configuring Endpoints1-3
185
Controlling Endpoints1-3 in
186
Endpoints1-3 in Interrupt or Bulk Mode
186
Endpoints1-3 in Isochronous Mode
187
Controlling Endpoints1-3 out
189
Endpoints1-3 out Interrupt or Bulk Mode
190
Endpoints1-3 out Isochronous Mode
190
24 Smbus
194
Figure 24.1. Smbus Block Diagram
194
Supporting Documents
195
Smbus Configuration
195
Smbus Operation
195
Figure 24.2. Typical Smbus Configuration
195
Arbitration
196
Clock Low Extension
196
Figure 24.3. Smbus Transaction
196
SCL Low Timeout
196
Transmitter Vs. Receiver
196
SCL High (Smbus Free) Timeout
197
Using the Smbus
197
Smbus Configuration Register
197
Figure 24.4. Typical Smbus SCL Generation
198
SFR Definition 24.1. SMB0CF: Smbus Clock/Configuration
200
SMB0CN Control Register
201
Hardware ACK Generation
201
Software ACK Generation
201
SFR Definition 24.2. SMB0CN: Smbus Control
202
Hardware Slave Address Recognition
203
SFR Definition 24.3. SMB0ADR: Smbus Slave Address
204
SFR Definition 24.4. SMB0ADM: Smbus Slave Address Mask
205
Data Register
206
SFR Definition 24.5. SMB0DAT: Smbus Data
206
Smbus Transfer Modes
207
Figure 24.5. Typical Master Write Sequence
207
Write Sequence (Master)
207
Figure 24.6. Typical Master Read Sequence
208
Read Sequence (Master)
208
Figure 24.7. Typical Slave Write Sequence
209
Write Sequence (Slave)
209
Read Sequence (Slave)
210
Smbus Status Decoding
210
Figure 24.8. Typical Slave Read Sequence
210
25 Uart0
215
Figure 25.1. UART0 Block Diagram
215
Enhanced Baud Rate Generation
216
Figure 25.2. UART0 Baud Rate Logic
216
Operational Modes
217
8-Bit UART
217
Figure 25.3. UART Interconnect Diagram
217
Figure 25.4. 8-Bit UART Timing Diagram
217
9-Bit UART
218
Figure 25.5. 9-Bit UART Timing Diagram
218
Multiprocessor Communications
219
Figure 25.6. UART Multi-Processor Mode Interconnect Diagram
219
SFR Definition 25.1. SCON0: Serial Port 0 Control
220
SFR Definition 25.2. SBUF0: Serial (UART0) Port Data Buffer
221
26 Uart1
223
Baud Rate Generator
223
Figure 26.1. UART1 Block Diagram
223
Table 26.1. Baud Rate Generator Settings for Standard Baud Rates
224
Data Format
225
Figure 26.2. UART1 Timing Without Parity or Extra Bit
225
Figure 26.3. UART1 Timing with Parity
225
Figure 26.4. UART1 Timing with Extra Bit
225
Configuration and Operation
226
Data Transmission
226
Data Reception
226
Figure 26.5. Typical UART Interconnect Diagram
226
Multiprocessor Communications
227
Figure 26.6. UART Multi-Processor Mode Interconnect Diagram
227
SFR Definition 26.1. SCON1: UART1 Control
228
SFR Definition 26.2. SMOD1: UART1 Mode
229
SFR Definition 26.3. SBUF1: UART1 Data Buffer
230
SFR Definition 26.4. SBCON1: UART1 Baud Rate Generator Control
231
SFR Definition 26.5. SBRLH1: UART1 Baud Rate Generator High Byte
231
SFR Definition 26.6. SBRLL1: UART1 Baud Rate Generator Low Byte
232
27 Enhanced Serial Peripheral Interface (SPI0)
233
Figure 27.1. SPI Block Diagram
233
Signal Descriptions
234
Master In, Slave out (MISO)
234
Master Out, Slave in (MOSI)
234
Serial Clock (SCK)
234
Slave Select (NSS)
234
SPI0 Master Mode Operation
235
Figure 27.2. Multiple-Master Mode Connection Diagram
235
Figure 27.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram
235
SPI0 Slave Mode Operation
236
Figure 27.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram
236
SPI0 Interrupt Sources
237
Serial Clock Phase and Polarity
237
Figure 27.5. Master Mode Data/Clock Timing
238
Figure 27.6. Slave Mode Data/Clock Timing (CKPHA = 0)
238
SPI Special Function Registers
239
Figure 27.7. Slave Mode Data/Clock Timing (CKPHA = 1)
239
SFR Definition 27.1. SPI0CFG: SPI0 Configuration
240
SFR Definition 27.2. SPI0CN: SPI0 Control
241
SFR Definition 27.3. SPI0CKR: SPI0 Clock Rate
242
SFR Definition 27.4. SPI0DAT: SPI0 Data
242
Figure 27.8. SPI Master Timing (CKPHA = 0)
243
Figure 27.9. SPI Master Timing (CKPHA = 1)
243
Figure 27.10. SPI Slave Timing (CKPHA = 0)
244
Figure 27.11. SPI Slave Timing (CKPHA = 1)
244
28 Timers
246
SFR Definition 28.1. CKCON: Clock Control
247
Timer 0 and Timer 1
248
Mode 0: 13-Bit Counter/Timer
248
Figure 28.1. T0 Mode 0 Block Diagram
249
Mode 1: 16-Bit Counter/Timer
249
Mode 2: 8-Bit Counter/Timer with Auto-Reload
249
Figure 28.2. T0 Mode 2 Block Diagram
250
Mode 3: Two 8-Bit Counter/Timers (Timer 0 Only)
250
Figure 28.3. T0 Mode 3 Block Diagram
251
SFR Definition 28.2. TCON: Timer Control
252
SFR Definition 28.3. TMOD: Timer Mode
253
SFR Definition 28.4. TL0: Timer 0 Low Byte
254
SFR Definition 28.5. TL1: Timer 1 Low Byte
254
SFR Definition 28.6. TH0: Timer 0 High Byte
255
SFR Definition 28.7. TH1: Timer 1 High Byte
255
Timer 2
256
16-Bit Timer with Auto-Reload
256
Figure 28.4. Timer 2 16-Bit Mode Block Diagram
256
8-Bit Timers with Auto-Reload
257
Figure 28.5. Timer 2 8-Bit Mode Block Diagram
257
Figure 28.6. Timer 2 Low-Frequency Oscillation Capture Mode Block Diagram
258
Low-Frequency Oscillator (LFO) Capture Mode
258
SFR Definition 28.8. TMR2CN: Timer 2 Control
259
SFR Definition 28.9. TMR2RLL: Timer 2 Reload Register Low Byte
260
SFR Definition 28.10. TMR2RLH: Timer 2 Reload Register High Byte
260
SFR Definition 28.11. TMR2L: Timer 2 Low Byte
260
SFR Definition 28.12. TMR2H Timer 2 High Byte
261
Timer 3
262
16-Bit Timer with Auto-Reload
262
Figure 28.7. Timer 3 16-Bit Mode Block Diagram
262
8-Bit Timers with Auto-Reload
263
Figure 28.8. Timer 3 8-Bit Mode Block Diagram
263
Figure 28.9. Timer 3 Low-Frequency Oscillation Capture Mode Block Diagram
264
Low-Frequency Oscillator (LFO) Capture Mode
264
SFR Definition 28.13. TMR3CN: Timer 3 Control
265
SFR Definition 28.14. TMR3RLL: Timer 3 Reload Register Low Byte
266
SFR Definition 28.15. TMR3RLH: Timer 3 Reload Register High Byte
266
SFR Definition 28.16. TMR3L: Timer 3 Low Byte
266
SFR Definition 28.17. TMR3H Timer 3 High Byte
267
29 Programmable Counter Array
268
Figure 29.1. PCA Block Diagram
268
PCA Counter/Timer
269
Table 29.1. PCA Timebase Input Options
269
PCA0 Interrupt Sources
270
Figure 29.2. PCA Counter/Timer Block Diagram
270
Capture/Compare Modules
271
Figure 29.3. PCA Interrupt Block Diagram
271
Edge-Triggered Capture Mode
272
Table 29.2. PCA0CPM and PCA0PWM Bit Settings for PCA Capture/Compare Modules
272
Figure 29.4. PCA Capture Mode Diagram
273
Software Timer (Compare) Mode
273
Figure 29.5. PCA Software Timer Mode Diagram
274
High-Speed Output Mode
274
Figure 29.6. PCA High-Speed Output Mode Diagram
275
Frequency Output Mode
275
8-Bit Pulse Width Modulator Mode
276
8-Bit, 9-Bit, 10-Bit and 11-Bit Pulse Width Modulator Modes
276
Figure 29.7. PCA Frequency Output Mode
276
9/10/11-Bit Pulse Width Modulator Mode
277
Figure 29.8. PCA 8-Bit PWM Mode Diagram
277
16-Bit Pulse Width Modulator Mode
278
Figure 29.9. PCA 9, 10 and 11-Bit PWM Mode Diagram
278
Watchdog Timer Mode
279
Figure 29.10. PCA 16-Bit PWM Mode
279
Watchdog Timer Operation
279
Figure 29.11. PCA Module 2 with Watchdog Timer Enabled
280
Watchdog Timer Usage
280
Register Descriptions for PCA0
281
SFR Definition 29.1. PCA0CN: PCA Control
282
SFR Definition 29.2. PCA0MD: PCA Mode
283
SFR Definition 29.3. PCA0PWM: PCA PWM Configuration
284
SFR Definition 29.4. Pca0Cpmn: PCA Capture/Compare Mode
285
SFR Definition 29.5. PCA0L: PCA Counter/Timer Low Byte
286
SFR Definition 29.6. PCA0H: PCA Counter/Timer High Byte
286
SFR Definition 29.7. Pca0Cpln: PCA Capture Module Low Byte
287
SFR Definition 29.8. Pca0Cphn: PCA Capture Module High Byte
287
30 C2 Interface
288
C2 Interface Registers
288
C2 Pin Sharing
295
Figure 30.1. Typical C2 Pin Sharing
295
Document Change List
296
Contact Information
298
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